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EDITED BYBILL TRAVIS & ANNEWATSON SWAGER

EDN DESIGN IDEAS

To generate high voltages with proper insulation between thehot node and the rest of the circuitry, a car ignition coil canfunction in place of a high-voltage transformer. These coils

have voltage ratings of approximately 20 kV, so you can usethem to produce voltages around this value. Because youknow the turns ratio of the coil, you can make a stable high-voltage source using a well-controlled voltage at the primaryside (Figure 1).

A high-voltage source is a useful device for many applica-tions, including when it is necessary to evaluate the conti-nuity of the dielectric coating deposited on a metal surface.

If you also want to estimate the breakdown strength of thecoating, this voltage source must be stable. You can easilygenerate the high voltage with the use of a step-up trans-

former, but the serious problem of proper insulation emerges.For voltages greater than a few kilovolts, specially construct-

ed transformers with the old insulation are often useful, butthese devices are rather expensive and bulky.

The main part of the generator in Figure 1 consists of a

free-running converter comprising Q1, Q

6, and the trans-

former, T1. During the first part of the conversion cycle, Q

1is

saturated, and energy stores in the magnetic field of T1. D

1is

reverse-biased during this time. In the second part of thecycle, Q

1is in cutoff, and the current from the secondary

winding of T1

forces D1

into conduction. During this time,energy pumps into C

1through part of the ignition coil, T

2.

This process allows the voltage, VC1

, on C1to build gradually

in a quantized manner. The value of the individual quan-tum, V

C1, is not constant and depends on the initial volt-

age, VCO

, which comes from the previous cycle, as follows:

whereis the energy stored in the magnetic field of T

1in the first cycle

25-kV generator tests insulationLUKASZ SLIWCZYNSKI AND PRZEMYSLAWKREHLIK, UNIVERSITY OF MINING AND METALLURGY, KRAKW, POLAND

10k

HIGH-VOLTAGE TIP25 kV

T2 (CAR'S IGNITION COIL)TURNS RATIO=93

VC1 C1 2 F/400V

NOTES: TRANSFORMER T1 DATA:PRIMARY WINDING: 23T, 0.5 mm.

SECONDARY WINDING: 500T, 0.5 mm.

CORE: EI-25.

LP(T1)=1.1 mH; LS(T1)=520 mHQ2, Q6, Q7, Q8=BC337.

Q3, Q4, Q5=BC307.

D1, D2=FR307 (FAST RECOVERY TYPE).TH1=MCR106-8, 2N6241 (600V, 4A).

562k 562k

Q R TR

DIS

THR CV

IC2

200

4.7 nF

15k

6

7

3

D1

D2TH1

IN-

4148

100k

470

560k

T1LP(T1)Q6

Q3

Q2200V200V

D3 D4

Q1BD911

330

R1 R2

100 nF

100 nF

4

1k

2

5

TL431

PGND15V

(TODEVICE

UNDER

TEST)

100 nF75

R3

1k1k

R4

270

Q7

TR

CV THR

Q

DIS

R

IC3

100 nF

5

2 3

7

6

4

1k

1k

1k

2.2 nF

3.9k

100 nF

4.7 F

Q8

1k

10k

D7

10k

Q4

2.2k

PUSHBUTTON SWITCH

D5D6

1k

2.2k

D9

12V

1N4004

1000 F330

9.1V

FUSE

470 nFLM555

IC1

10k

150

10k 10k

LM555

330

Q5

FIGURE 1

Using a cars ignition coil produces a test voltage as high as 25 kV for insulation testing.

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EDN DESIGN IDEAS

and ICMAX(Q1)

is the collector current of Q1

at the end of thefirst cycle. For the component values in Figure 1, E

C0.5

mJ, and ICMAX(Q1)

1A.R

1, R

2, and R

3divide down V

C1. When this reduced voltage

reaches 2.5V, the TL431s 2.5V reference starts to sink the cur-rent through R

4, so the voltage at the trigger input of the one-

shot, IC2, rapidly decreases. An output pulse from IC

2stops

the converter for about 8 msec; the emitter node of Q6

goeshigh, driving it into cutoff. The rising edge of IC

2s output

pulse also triggers thyristor TH1. The thyristor connects C

1,

which is charged to the appropriate voltage, directly to theprimary winding of the ignition coil, and the high-voltage

pulse appears at the hot end of the coil. A damped oscilla-tion also starts because the ignition coil and C

1form a reso-

nant circuit.When a path between the hot end and ground exists,

part of the energy from the capacitor disperses in the electric

arc, and the rest returns to the capacitor through D2. When

there is no path from this end of the current to flow, almostall of the energy pumps back into C

1. This scheme provides

the circuit with relatively high efficiency.You can calculate the voltage at the hot side using the

following formula:where N

SEC(T2)/N

PRI(T2)is the turns ratio of the ignition coil,

which equals 93 in this case. Changing the value of R3con-

veniently regulates VHIGH. The accuracy of this voltage is in

the range of one quantum VC1

multiplied by T2s turns

ratio. Thus, VC1

should be small to achieve good stabiliza-tion. On the other hand, a smaller value increases the time

between subsequent high-voltage pulses. In this case, theaccuracy estimate of the high-voltage pulse is better than0.5% at 25 kV.

The free-running frequency of the converter depends onthe time it takes to lead Q

1

out of saturation (first part of thecycle) and the time when the current from the secondarywinding of T

1drops to a value near zero (second part of the

cycle). This circuit doesnt tightly control this frequency,which isnt a critical design parameter; the values in Figure1 set the frequency to approximately 6 kHz.

Q2, D

3, and D

4prevent V

C1from exceeding about 400V,

which protects the generator from producing excessivelyhigh voltages. Q

3, Q

4, Q

5, and associated circuitry allow for

blocking the converter when the power supply to the circuitis too low. A too-low power-supply level may lead to an out-

put-pulse amplitude from IC2

that is too low to trigger thethyristor, so V

C1may reach a very high value, limited only by

the breakdown voltage of the thyristor. This breakdown volt-

age is the second level of protection, but you can never taketoo much care in circuits like these.

Two LEDs indicate the status of the power supply: D5indi-

cates that the level is OK, and D6, that the power supply is too

low. One-shot IC3, Q

4, and associated components form the

source of an alarm, indicated by a flashing D7, when the iso-

lation breaks down or a discontinuity occurs. A simple push-button switch turns on the generator.

For the component values in Figure 1, the circuit gener-ates 25-kV pulses with a repetition rate of approximately 0.2sec. This repetition rate depends on the occurrence or lack ofoccurrence of the electric arc. Because the amount of energystored in C

1is relatively low, the energy of the high-voltage

pulse is also low, which is good for safety purposes. Note thatit is very important and absolutely necessary to connect thepart youre testing to the PGND point, because the risk ofelectric shock exists. (DI #2199) e

To Vote For This Design, Circle No. 414

,CV

E1

CV

E21VV

10C

C

12

0C

C0C1C

+=

2

ILE

2

)1Q(CMAX)1T(P

C

=

,N

N1

R

RR15.2V

)2T(PRI

)2T(SEC

3

21HIGH

+

++=

The DS5000T (Dallas Semiconductors, www.dalsemi.com) is

an 8051-compatible processor that integrates nonvolatilememory and a real-time clock. This module has an impres-sive set of functional extensions and security features, whichmakes it particularly useful for all-in-one embedded systems.

Unfortunately, access to the real-time clock is complicatedand thus inefficient. You access the on-chip real-time-clockregisters serially in secondary address space by selecting theECE2 bit in the MCON register. Instead of just moving the

data, you must execute MOVX instructions with appropriateaddress patterns. First, a 64-bit key is necessary to open theclock, followed by a read or write of the next 64 bits of

date/time data. The access routines available from the man-

ufacturer (example file DEMODS5T.SRC) are painfully slow:a byte read takes 106 processor cycles, a byte write takes 112cycles, and clock opening takes 1929 cycles. Therefore, accessto all real-time-clock registers (open/read or open/writesequences) lasts more than 2800 cycles.

Listing 1 uses a different control scheme; the protocollogic resets only during system start-up, which consumes 436cycles. Also, the listing linearizes the short loops used in the

original procedures to open the clock and read/write the databyte. The result is that a byte read takes 51 cycles, a byte writetakes 57 cycles, a whole real-time-clock read takes 926 cycles,

Scheme speeds access toPs real-time clockJERZYCHRZASZCZ, WARSAWUNIVERSITY OF TECHNOLOGY, WARSAW, POLAND

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EDN DESIGN IDEAS

and a real-time-clock write takes 972 cycles. The potentialdrawback of this option, with respect to the original

approach, is that interrupt-service routines executed duringreal-time-clock access must not address external data memo-ry, because any MOVX would interfere with the clock-accessprotocol.

You can downloadListing 1 and other related listings from

EDNs Web site, www.ednmag.com. At the registered-user

area, go into the Software Center to download the file fromDI-SIG, #2187. (DI #2187) e

To Vote For This Design, Circle No. 415

LISTING 1REAL-TIME-CLOCK-ACCESS ROUTINE

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EDN DESIGN IDEAS

+VS

GND

REF01

VO

15V

0.10.01

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

IC1

4

MSB LSB

6 1410V

R15k

R318k

R24k

R42k

10k

5k

10k 5k

10k

10k

VS VS

IC2DAC08 IC3

OPA111

R610k

R510k

IC4AOP271

IC4B

Q2

Q1

5k

IREF

D7 D6 D5 D4 D3 D2 D1 D0VREF(+)

VREF( )IOUT

IOUT

VOUT

VIN

D2

D1

1N914

1N914

IOUTVLIOUT

VREF (10V)

15

15V15V

15V

VL

15V

15V

13 163

3

3

7

1

2

2

1

6

5

4

2

6

4 4

5 6 7 8 9 10 11 12

COMP VLC

+

+

+

15V

8

NOTE: ALL CAPACITORS ARE IN MICROFARADS.

7

2

FIGURE 1

Amplitude limiters are necessary in many systems, such asradar and FM receivers, for which the system cannot allowthe amplitude of the signal to exceed the given positive, neg-

ative, or both limits. In the circuit in Figure 1, amplifier IC4B

smaximum output is digitally programmable over 2 to 10Vin 2n steps, where n is the number of bits of the DAC. IC

1, a

precision 10V reference, provides a full-scale reference cur-rent, I

REF=V

REF/R

1=2 mA, to IC

2, a multiplying DAC.

IC3s output voltage, V

L, is the sum of the product of the

digital word and unipolar reference voltage and IC1s dc off-

set as follows:

where N can assume values of 0 to 2n1.When all digital inputs are set to a logic low, N=0,

For the values of R3, R

4, and V

REFin this example, V

L(MIN)=1V.

When all the digital inputs are set to logic high (n=8, andN=255),

For the values of R1and R

2, V

L(MAX)9V.

Within the limiting levels, the amplifier does not modifyits input signal but provides a gain of A

V=R

6/R

5. As V

OUTrises

above VL+1Vadding 1V overcomes the potential drops of

the base-emitter junctions of Q1

and D1the base-emitter

junction of Q1becomes forward-biased, allowing the collec-

tor current to flow to the summing node, thus limiting VOUT

.A similar action occurs with Q

2and D

2as V

OUTgoes below

VL1V.

You can thus program the limiting levels or the maximumoutput voltage of the amplifier symmetrically over V

L(MIN)+1V

to VL(MAX)

+1V with a resolution of [(VL(MAX)

+1)(VL(MIN)

+1V)]/2nV in accordance with the 8-bit digital-input binary word.

The circuit becomes a programmable positive/negative limit-

ing amplifier if you remove the appropriate diode-transistorpairs from the feedback. (DI #2201) e

To Vote For This Design, Circle No. 416

Limiting amplifier is digitally programmableV MANOHARAN, NAVAL PHYSICAL AND OCEANOGRAPHIC LABORATORY, KOCHI, INDIA

The maximum output of this amplitude limiter is digitally programmable over 2 to 10V in 2n steps, where n is the numberof bits of the DAC.

,VRR

RR

2

N

R

VV REF

43

42n

1

REFL +

+

=

.VRR

RV REF

43

4)MIN(L +=

.V1R256

255

R

V

VRR

R

R2

12

R

V

V

2

1

REF

REF43

4

2n

n

1

REF

)MAX(L

+=

++

=

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EDN DESIGN IDEAS

Dot-matrix LEDs find wide use in advertising displays. Prod-ucts now on the market range from an inexpensive 58 (row-by-column) single-color LED to an expensive 88 RGB

device. The method provided here allows you to obtain morethan three main colors from an 88 tricolor LED. In fact, tri-color dot-matrix LEDs have only two LED diesred andgreen. When you apply current to one, you obtain a red or agreen color. When you apply current to both, orange results.

The circuit in Figure 1, used in conjunction with the MCS-51 code in Listing 1, works efficiently in controlling the LEDto generate various shades of the three colors.

To add tones or shades of the main colors to the tricolorLED, you do not need to modify the circuit in Figure 1; youneed only consider the software. Software modifications con-

sist of adding more color planes or pages of display buffer,adding memory locations (mapped onto the LED dots), andincreasing the number of refresh times, in which the con-troller updates all LED dots to cover all added color planes.

For example, if you decide to use four color planes, dividedinto two red and two green planes, for dot i of the dot-matrixLED, youll obtain the shades listed in Table 1 .

In addition, by allocating eight color planes (four red and

Get more than three colors from a dot-matrix LEDW KURDTHONGMEE, NAKORN SI THAMMARAT, THAILAND

A few TTL circuits and some MCS-51 code allow you to obtain more than three colors from a tricolor dot-matrix LED.

DB0DB1

DB2DB3DB4DB5DB6DB7

DB0DB1

DB2DB3DB4DB5DB6DB7

SN74HC574

IC1

1918

171615141312

1817

161514131211

12

345678

1 9

11

23

456789

C

1D

2D3D4D5D6D7D8D

OC

1Q

2Q3Q4Q5Q6Q7Q8Q

ULN2803

IC2 LED1

COM

1P

2P3P4P5P6P7P8P

COM0

COM1COM2COM3COM4COM5COM6COM7

838 COMMON-CATHODE LED

P/CSYSTEM

RED

SN74HC574

1Q

2Q3Q4Q5Q6Q7Q8Q

R0

19 18 17 16 15 14 13 12

2CS1

CS2

11 3 4 5 6 7 8 9

R1 R2 R3 R4 R5 R6 R7

1Q

1

2Q 3Q 4Q 5Q 6Q 7Q 8Q

1DC 2D 3D 4D 5D 6D 7D 8D

GREEN

CS0

DB0 DB1 DB2 DB3 DB4 DB5DB6 DB7

SN74HC574IC3IC3

G0

19 18 17 16 15 14 13 12

211 3 4 5 6 7 8 9

G1 G2 G3 G4 G G6 G7

1Q

1

OC 2Q 3Q 4Q 5Q 6Q 7Q 8Q

1D 2D 3D 4D 5D 6D 7D 8D

OC

DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

C

FIGURE 1

Red 1 Red 2 Green 1 Green 2 Color

0(1) 1(0) 0 0 Red 50%

1 1 0 0 Red 100%

0 0 0(1) 1(0) Green 50%

0 0 1 1 Green 100%

0(1) 1(0) 0(1) 1(0) Orange 50%

1 1 1 1 Orange 100%

0 0 0 0 Blank

TABLE 1VALUE IN COLOR PLANEMAPPED TO DOT I

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EDN DESIGN IDEAS

four green), you can obtain the color

shades listed in Table 2. Note that onlythe number of ones in the color planescontrols color appearance. Therefore,the permutations do not change thecolor, as long as the numbers of ones inTable 2 remain constant. For example,the values 0110, 1001, 1100, and 0011

for R1 through R4 all produce the samecolor: orange 50%. You can downloadListing 1as well as the MCS-51 codethat produces 13 colors from an 88 tri-color LEDfrom EDNs Web site,www.ednmag.com. At the registered-user area, go to the Software Center todownload the file from DI-SIG #2195.

Note that, in practice, bytewide out-put ports control the LED. To assign acolor to a dot, the routine must extract

a bit from a byte and then assign the bitvalue of the selected color plane byplane. (DI #2195) e

To Vote For This Design, Circle No. 417

LISTING 1MCS-51 CODE FOR SIX COLORS FROM A TRICOLOR LED

Red 1 Red 2 Red 3 Red 4 Green 1 Green 2 Green 3 Green 4 Color

0 0 0 1 0 0 0 0 Red 25%

0 0 1 1 0 0 0 0 Red 50%0 1 1 1 0 0 0 0 Red 75%

1 1 1 1 0 0 0 0 Red 100%

0 0 0 0 0 0 0 1 Green 25%

0 0 0 0 0 0 1 1 Green 50%

0 0 0 0 0 1 1 1 Green 75%

0 0 0 0 1 1 1 1 Green 100%

0 0 0 1 0 0 0 1 Orange 25%

0 0 1 1 0 0 1 1 Orange 50%

0 1 1 1 0 1 1 1 Orange 75%

1 1 1 1 1 1 1 1 Orange 100%

0 0 0 0 0 0 0 0 Blank

TABLE 2VALUE IN COLOR PLANE MAPPED TO DOT I

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7/8128 EDN MAY7, 1998

EDN DESIGN IDEAS

Many Cs, such as the 8051 and the 68HC11, can support aninth data bit on the asynchronous serial port. This bit is use-ful in multidrop applications in which you can use it to

denote an address on the serial bus, as opposed to data des-tined for a particular address. The UART used in IBM PCs (andclones) does not directly support this operating mode. How-ever, through some software manipulation, you can add thePC to a serial bus and integrate it into a ninth-bit system,albeit with some limitations.

The method differs for data reception and transmission. Asa result, the PC can work only in half-duplex mode. Because

half-duplex communication is common practice on PC net-works, this limitation is not a significant drawback. The tech-nique also requires that the CPU check each incoming byte

for the ninth bit. (You can usually configure aC to generatean interrupt when the ninth bit is set.) For the PC to receivethe nine bits, it is necessary to treat the ninth bit as a paritybit. Although its impossible to read the parity bit in the PCsUART directly, it is possible to analyze the received data byte

and determine what the parity should be.If analysis reveals a parity error, then the value of the ninth

bit is opposite to the calculated parity. If no error exists, thenthe value of the ninth bit is equal to the calculated parity. Inthe 16550 UART, the FIFO includes the three error bits witheach data byte, so the parity error (or lack thereof) is always

associated with the current data byte. It is possible, however,to disable the FIFO feature. The technique for transmission isslightly different. The 8250/16450/16550 UART has a forced-parity format (also known as a stick parity), in which you

can set the parity to a one or to a zero. You do this by settingbit 5 (stick parity) and bit 3 (parity enable) in the UARTs line-control register (LCR). The transmitted parity bit is then thelogical inverse of bit 4 of the LCR.

In the sample code in Listing 1 , address 0xff (with bit 9set) is reserved and used to indicate the last byte of the trans-mission. The first byte of the transmission is an address, and

it transmits with bit 9 set. The RS-232C port connects to anRS-232C/RS-485 converter, where the RTS line controls thedirection. The code given here is not interrupt-driven, but

you could implement it as an interrupt-driven routine. Thecode comprises three modules: background (back.cpp), serialprocedures (serial.cpp), and memory declaration (mem.cpp).Note that mem.cpp declares one include file (mem.h) for thepublic memory. You can download the files from EDNs Web

site, www.ednmag.com. At the registered-user area, go to theSoftware Center to download the files from DI-SIG #2198.(DI #2198) e

To Vote For This Design, Circle No. 418

Implement a nine-data-bit UART on a PCAUBREYKAGAN, WEIDMULLER LTD, MARKHAM, ON, CANADA

LISTING 1BACKGROUND CODE FOR NINTH-BIT TRANSMISSION

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Entry blank must accompany all entries. $100 Cash Award

for all published Design Ideas. An additional $100 CashAward for the winning design of each issue, determinedby vote of readers. Additional $1500 Cash Award forannual Grand Prize Design, selected among biweekly win-ners by vote of editors.

To: Design Ideas Editor, EDN Magazine275 Washington St, Newton, MA 02158

I hereby submit my Design Ideas entry.

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Title

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My e-mail address may be published Yes No

Company

Address

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Design Idea Title

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Entry blank must accompany all entries. (A sepa-rate entry blank for each author must accompany everyentry.) Design entered must be submitted exclusively toEDN, must not be patented, and must have no patentpending. Design must be original with author(s), mustnot have been previously published (limited-distributionhouse organs excepted), and must have been construct-ed and tested. Fully annotate all circuit diagrams. Pleasesubmit software listings and all other computer-readabledocumentation on a IBM PC disk in plain ASCII.

Exclusive publishing rights remain with Cahners Pub-

lishing Co unless entry is returned to author, or editorgives written permission for publication elsewhere.In submitting my entry, I agree to abide by the rules of

the Design Ideas Program.

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Your vote determines this issues winner.Vote now,by circling the appropriate number on the readerinquiry card.

EDN DESIGN IDEAS