b « U f PLD/FPGA¯编程逻辑基础.pdf · FPGA f 2 16-bit SR flip-flop clock mux y q e a b c d...
Transcript of b « U f PLD/FPGA¯编程逻辑基础.pdf · FPGA f 2 16-bit SR flip-flop clock mux y q e a b c d...
![Page 1: b « U f PLD/FPGA¯编程逻辑基础.pdf · FPGA f 2 16-bit SR flip-flop clock mux y q e a b c d 16x1 RAM 4-input LUT clock enable set/reset • Xilinx CLB/SLICE • Altera LE •](https://reader035.fdocumentos.com/reader035/viewer/2022062607/60529770ca6a4e5dca0a4139/html5/thumbnails/1.jpg)
PLD/FPGA
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» PLD/FPGA» PLD/FPGA»» FPGA» FPGA» FPGA
» FPGA
IP cores
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» - »» /»
ASICsApplication Specific Integrated Circuits
ASSPMicroprocessors Microcontrollers
FPGA & CPLD
FPGA
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PLDA B C
Flip-flop
SelectEnable
D Q
Clock
AND plane
MUX
1f
SPLD / /
CPLD SPLD
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FPGA
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FPGA
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
• Xilinx CLB/SLICE• Altera LE• Lattice: LUTs/LCs
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» & & DSP
» PLL DLL
» IO DDR
» MAC
» RAM FIFO
» I2C SPI
» ADCs
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Altera
FPGA Stratix Arria Cyclone
PLD MAX II MAX V MAX10
Enpirion PowerSoc DC DC
IP Core
NIOS II ColdFire V1 ARM Cortex M
ARM Cortex A9
Quartus II
![Page 9: b « U f PLD/FPGA¯编程逻辑基础.pdf · FPGA f 2 16-bit SR flip-flop clock mux y q e a b c d 16x1 RAM 4-input LUT clock enable set/reset • Xilinx CLB/SLICE • Altera LE •](https://reader035.fdocumentos.com/reader035/viewer/2022062607/60529770ca6a4e5dca0a4139/html5/thumbnails/9.jpg)
![Page 10: b « U f PLD/FPGA¯编程逻辑基础.pdf · FPGA f 2 16-bit SR flip-flop clock mux y q e a b c d 16x1 RAM 4-input LUT clock enable set/reset • Xilinx CLB/SLICE • Altera LE •](https://reader035.fdocumentos.com/reader035/viewer/2022062607/60529770ca6a4e5dca0a4139/html5/thumbnails/10.jpg)
Altera MAX10
![Page 11: b « U f PLD/FPGA¯编程逻辑基础.pdf · FPGA f 2 16-bit SR flip-flop clock mux y q e a b c d 16x1 RAM 4-input LUT clock enable set/reset • Xilinx CLB/SLICE • Altera LE •](https://reader035.fdocumentos.com/reader035/viewer/2022062607/60529770ca6a4e5dca0a4139/html5/thumbnails/11.jpg)
Xilinx
FPGAFabless
FPGA Virtex Kintex ArtixZYNQ SoCPLD CoolRunner 9500
Xilinx ISEVivado Design Suite
![Page 12: b « U f PLD/FPGA¯编程逻辑基础.pdf · FPGA f 2 16-bit SR flip-flop clock mux y q e a b c d 16x1 RAM 4-input LUT clock enable set/reset • Xilinx CLB/SLICE • Altera LE •](https://reader035.fdocumentos.com/reader035/viewer/2022062607/60529770ca6a4e5dca0a4139/html5/thumbnails/12.jpg)
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Xilinx ZYNQ
![Page 14: b « U f PLD/FPGA¯编程逻辑基础.pdf · FPGA f 2 16-bit SR flip-flop clock mux y q e a b c d 16x1 RAM 4-input LUT clock enable set/reset • Xilinx CLB/SLICE • Altera LE •](https://reader035.fdocumentos.com/reader035/viewer/2022062607/60529770ca6a4e5dca0a4139/html5/thumbnails/14.jpg)
Lattice Semi
FPGA PLD
iCE MachXO ECP
Power Manager Platform Manager
ispClock
Lattice Diamond
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Actel(MicroSemi)
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» IO
DSP
»
»
»
» RAM
»
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Lattice MachXO2 FPGA
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HDL VHDL, Verilog, C, Simulink)
Synthesis HDL FPGA
Place & Route
(Bit-File)
FPGA
-
(Modelsim)
(Modelsim)
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» /
» vs PLL vs DLL
»
» JTAG
» IO
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» IP Core IP
»
» TestBench
»
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• / • • /
IP Cores
• • •
• • • /
• FAE • • /
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MACHXO2
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✦ FPGA LCMXO2-1200HC-4MG132✦ USB 5V✦ 25MHz✦ 3 LED LED✦ 2✦ 2 RGB LED✦ I2C✦ SPI✦ JTAG✦ 29 GPIO
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LCD (SPI)
FPGA
1 2 3 4
ON
ADC(SPI)
DAC(SPI)
• FPGA
• Verilog
•
• LED LCD
• DDS
• ADC
• SPI I2C
•
• FPGA IP
• ROM FIFO
• 8
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