E

E#

A

instrução – 0dados - 1

ler – 1escrever - 048 MHz

G12F13F12E14E13D15D14C16

LCD

D(7:0)

(H15,F16,H13)

Ad

dre

ss

(2:0

)

G13 G14

E E#

D16Read(1)

Writ

e(0)

botões

10

01

S1 ...S

8L

1 L2 L

3 L4

B4

B1

case idx iswhen 0=> ext_a<= "00" & rs;when 1=> cs <= '1';ext_d<= cmd;when 2=> cs <= '0';when 3=> null;

end case;

1. instrução/informação

2. dados

3. activar LCD

4. não faz nada

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;

entity lcd isport (

clk48: in std_logic;rst: in std_logic;ext_a: out std_logic_vector(2 downto 0);ext_d: out std_logic_vector(7 downto 0);ext_rw: out std_logic;cs_lcd: out std_logic;csn_lcd: out std_logic );

end lcd;

--------------------------------------------------------------------------------

------------------------------------------------------------------ 2003 by Valery Sklyarov and Iouliia Skliarova-- DETUA, IEETA, Aveiro University, Portugal ------------------------------------------------------------------ in this example a part of VHDL code from Trenz electronic was used------------------------------------------------------------------ Interaction with HD44780U Dot Matrix LCD controller/driver-- LCD 2 lines x 16 characters----------------------------------------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Hitachi_lcd isport (

clk48: in std_logic; -- clock 48 MHzrst: in std_logic; -- resetext_a: out std_logic_vector(2 downto 0); -- LCD controlext_d: out std_logic_vector(7 downto 0); -- LCD dataext_rw: out std_logic; -- LCD read/writecs_lcd: out std_logic; -- LCD chip select active highcsn_lcd: out std_logic -- LCD data direction

);end Hitachi_lcd;

--------------------------------------------------------------------------------architecture Behavioral of Hitachi_lcd is

signal clk: std_logic; -- local clocksignal div: unsigned (14 downto 0); -- local clock divider signal reset: std_logic; -- lcd reset sequence active

signal cmd: std_logic_vector (7 downto 0); -- data/command to lcdsignal rs: std_logic; -- register select bit for lcdsignal idx: integer range 0 to 3; -- sequencer index for lcd timingsignal cs: std_logic; -- chip select for lcdsignal cnt: unsigned (5 downto 0); -- character, command counter

constant line1: string(1 to 16):= "LCD operations :"; -- strings to displayconstant line2: string(1 to 4):= "DEMO";

begin

process(clk48, rst) -- local clock generatorbegin

if rst= '1' thendiv <= (others=> '0');

elsif rising_edge(clk48) thendiv<= div + 1;

end if;end process;

clk<= div(div'left);

process(clk, rst) -- LCD sub-clocks sequencerbegin

if rst= '1' then idx <= 0;

elsif rising_edge(clk) thenif idx= 3 then idx<= 0; else idx<= idx + 1; end if;

end if;end process;

process(clk, rst) -- LCD local control signals generatorbegin

if rst= '1' thencs <= '0';ext_a <= (others=> '0');ext_d <= (others=> '0');elsif rising_edge(clk) then case idx is

when 0=> ext_a<= "00" & rs; -- set register addresswhen 1=> cs <= '1';ext_d<= cmd; -- write data, activate chip selectwhen 2=> cs <= '0'; -- deactivate chip select when 3=> null; -- data hold time

end case;end if;

end process;ext_rw<= '0'; -- always write to LCDcs_lcd <= cs; -- chip select for LCDcsn_lcd<= '0'; -- always write to LCD

process(clk, rst)begin

if rst= '1' thencmd <= x"02"; -- clear DDRAM counter, switch off shiftrs <= '1';reset <= '1'; -- activate LCD initialization from the beginningcnt <= (others => '0');

elsif rising_edge(clk) thenif idx = 2 then cnt <= cnt + 1;end if;if (reset ='0') then -- normal functionality after initialization

case cnt is when "000000" => cmd <= x"80"; rs <= '0';-- DDRAM address to the beginning of the first line when "000001" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(1)), 8)); rs <= '1'; when "000010" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(2)), 8)); rs <= '1'; when "000011" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(3)), 8)); rs <= '1'; when "000100" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(4)), 8)); rs <= '1'; when "000101" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(5)), 8)); rs <= '1'; when "000110" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(6)), 8)); rs <= '1'; when "000111" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(7)), 8)); rs <= '1'; when "001000" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(8)), 8)); rs <= '1'; when "001001" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(9)), 8)); rs <= '1'; when "001010" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(10)), 8)); rs <= '1'; when "001011" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(11)), 8)); rs <= '1'; when "001100" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(12)), 8)); rs <= '1'; when "001101" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(13)), 8)); rs <= '1'; when "001110" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(14)), 8)); rs <= '1';

when "001111" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(15)), 8)); rs <= '1'; when "010000" => cmd <= std_logic_vector(to_unsigned(character'pos(line1(16)), 8)); rs <= '1'; when "010001" => cmd <= x"C0"; rs <= '0';-- DDRAM address to the beginning of the second line when "010-1-"|"0101--" => cmd <= x"20"; rs <= '1'; when "011000" => cmd <= std_logic_vector(to_unsigned(character'pos(line2(1)), 8)); rs <= '1'; when "011001" => cmd <= std_logic_vector(to_unsigned(character'pos(line2(2)), 8)); rs <= '1'; when "011010" => cmd <= std_logic_vector(to_unsigned(character'pos(line2(3)), 8)); rs <= '1'; when "011011" => cmd <= std_logic_vector(to_unsigned(character'pos(line2(4)), 8)); rs <= '1'; when "0111--"|"10000-" => cmd <= x"20"; rs <= '1'; when "100010" => cmd <= x"80"; rs <= '0'; when others => cmd <= x"80"; rs <= '0';--cnt <= "000000";end case;

else -- initialization of LCD from the beginningcase cnt is -- delay such as from "000000" to "001000" is important

-- for satisfying LCD timing requirements when "000000" => cmd <= x"38"; rs <= '0'; -- (x"20" Function Set)|(x"10" 8-bit data)|

-- (x"08" two lines) when "001000" => cmd <= x"0C"; rs <= '0'; -- (x"08" display control)|(x"04" display on)|

-- (x"00" cursor off - our case; x"02" cursor on) when "010000" => cmd <= x"06"; rs <= '0'; -- (x"04" entry mode set)|(x"02" increment on) when "011000" => cmd <= x"01"; rs <= '0'; -- (x"01" clear display and DDRAM counter) when "100000" => reset <= '0'; cnt <= "000000"; -- initialization is finished when others => null;end case;

end if; end if;end process;end Behavioral;

VHDL Reserved Word: constant

Purpose

A class of data object. Constants can hold a single value of a given type. If the value is not specified, the constant is a deferred constant, andcan appear inside a package declaration only.

Syntax

constant_declaration ::= constant identifier_list : subtype_indication [:= expression];

Example

constant alpha : character := 'a';

Example, deferred constant

constant no_of_outputs : integer;

constant line1: string(1 to 16):= "LCD operations :"; -- strings to display

VHDL Reserved Word: null

Purpose

Sequential statement that causes no action to take place;execution continues with the next statement.

Syntax

null_statement ::= [label :] null;

Example

if (sum >= 100) then p1 : null

B”1111” – binary bit vector literalO”353” – octal bit vector literalX”A5” – hexadecimal bit vector literal

Scalar Types

EnumeratedCharacter (literals: 128 characters of the ASCII character set)BitBoolean (literals: true, false)Severity_level (literals: note, warning, error, failure)NumericIntegerPhysicalFloating_point

Signal attribute 'pos' indicates thatunspecified logic should be giventhe value of 0.

when "01111" => lcdout <= std_logic_vector(to_unsigned(character'pos(line2(1)), 8));