Exame de Eletronica Aplicada EE532

Prof. Candido

10 de julho de 2013

Nome:RA:

Marque V (verdadeiro) ou F (falso) no quadro derespostas abaixo. Cada acerto vale 0,4 ponto. Errosnao anulam acertos.Nao se apresse em responder as questoes; analise-as

com atencao e cuidado.

V F1.11.21.31.42.12.22.32.43.13.23.33.44.14.24.34.44.55.15.25.35.46.16.26.36.4

Tabela 1: Quadro de respostas.

1. Considere o circuito a seguir e o modelo da tensaoconstante para os diodos.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 119 (1)

Sec. 3.6 Chapter Summary 119

1D

VB

D R1

inV

1

D R2

outV

D2

R2

VB

R1

inV

D

outV

D2

R1

inV

D

outV

R2

VB

D2

inV

VB

R1

R2

outV

(c)

(a) (b)

(d)

1 1

1

Figure 3.77

1D

inV

R

outV

= 1 k!1

1D

inV

R

outV

= 1 k!1

D2

1D

inV outV

D2! 1 k

R1inV outV

D2!2 k! 1 k

R1

R2

(c)

(a) (b)

(d)

Figure 3.78

37. A 3-V adaptor using a half-wave rectifier must supply a current of 0.5 A with a maximum

ripple of 300 mV. For a frequency of 60 Hz, compute the minimum required smoothing

capacitor.

38. Assume the input and output grounds in a full-wave rectifier are shorted together. Draw the

output waveform with and without the load capacitor and explain why the circuit does not

operate as a rectifier.

39. Plot the voltage across each diode in Fig. 3.38(b) as a function of time if .

Assume a constant-voltage diode model and .

40. While constructing a full-wave rectifier, a student mistakenly has swapped the terminals of

as depicted in Fig. 3.82. Explain what happens.

41. A full-wave rectifier is driven by a sinusoidal input , where V

and . Assuming mV, determine the ripple amplitude with a

1000- F smoothing capacitor and a load resistance of 30 .

42. Suppose the negative terminals of and in Fig. 3.38(b) are shorted together. Plot the

input-output characteristic assuming an ideal diode model and explaining why the circuit

does not operate as a full-wave rectifier.

(1.1) D2 nunca conduz com D1 cortado.

(1.2) Existe uma faixa de Vin para a qual ape-nas D1 conduz, quando entao Vout = (Vin VD,on)[R2/(R1 +R2)].

(1.3) Quando Vin > 2VD,on + VB , D1 e D2 con-duzem, e Vout = VB + VD,on.

(1.4) Quando Vin < 2VD,on+VB , D1 eD2 cortam,e Vout = 0.

2. Considere o circuito a seguir.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 120 (1)

120 Chap. 3 Diode Models and Circuits

1D

R

outV

= 1 k!1

1D

R

outV

= 1 k!1

D2

1D

outV

D2! 1 k

R1outV

D2!2 k! 1 k

R1

R2

(c)

(a) (b)

(d)

I in I in

I in I in

Figure 3.79

C1

1D

0.5 V

outVinV

Figure 3.80

C1

1D

0.5 V

outVinV

Figure 3.81

D1

D2 D

D

3

4

RL

Vin

Vout

Figure 3.82

43. Suppose in Fig. 3.43, the diodes carry a current of 5 mA and the load, a current of 20 mA. If

the load current increases to 21 mA, what is the change in the total voltage across the three

diodes? Assume is much greater than .

44. In this problem, we estimate the ripple seen by the load in Fig. 3.43 so as to appreciate

the regulation provided by the diodes. For simplicity, neglect the load. Also, Hz,

F, , and the peak voltage produced by the transformer is equal to 5

V.

(a) Assuming carries a relatively constant current and mV, estimate the

ripple amplitude across .

(b) Using the small-signal model of the diodes, determine the ripple amplitude across the

load.

(2.1) Durante o ciclo negativo da entrada, D1 eD3 conduzem, e Vout = 0.

(2.2) Durante o ciclo negativo da entrada, D1 eD2 conduzem, e Vout = Vin.(2.3) Durante o ciclo positivo da entrada, D2 eD3 cortam, e Vout = 0.

(2.4) Trata-se de um retificador de onda completa,assim chamado por converter ambos os ciclos daentrada (positivo e negativo) numa mesma polari-dade de sada.

3. Considere o circuito a seguir, no qual os transisto-res tem mesmo e mesmo IS .

(3.1) O transistor Q1 opera como fonte de cor-rente.

(3.2) Desprezado o efeito Early, a impedancia (depequenos sinais) vista olhando-se para dentro dabase de Q2 (veja indicacao na figura) e aproxima-damente 2r.

Jos Cndido S. Santos Filho

Jos Cndido S. Santos Filho

Jos Cndido S. Santos Filho

Jos Cndido S. Santos Filho

Jos Cndido S. Santos Filho

Jos Cndido S. Santos Filho

(3.3) Inicialmente, para o calculo das correntes etensoes de polarizacao, podemos assumir que Q1esta no modo ativo direto. No entanto, apos oscalculos, pode ocorrer de verificarmos que Q1 estade fato saturado. Nesse caso, devemos entao refa-zer os calculos adotando o modelo de Q1 em sa-turacao.(3.4) A corrente de polarizacao IC de am-bos os transistores e dada pela solucao daequacao IC/ = 2VT ln(IC/IS)/32k [VCC 2VT ln(IC/IS)]/18k.

4. Considere o amplificador a seguir.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 369 (1)

Sec. 7.6 Chapter Summary 369

M

VDD

R

inVC1

G C2

outV

RD

1

= 1.8 V

Figure 7.82

M 1

VDD = 1.8 V

R1

R2

C1

inV

RDoutV

RS

Figure 7.83

C

M 1

VDD = 1.8 V

R1C1

inV

RDoutV

RS S

Figure 7.84

VDD

M 1

M 2

outV

inV

Vb

= 1.8 V

Figure 7.85

gain of 20 and a power budget of 2 mW. Assume for both transistors and

the maximum allowable level at the output is 1.5 V (i.e., must remain in saturation if

V).

64. Consider the circuit shown in Fig. 7.86, where is very large and V .

(a) Calculate the voltage gain.

(b) Design the circuit for a voltage gain of 15 and a power budget of 3 mW. Assume

and the dc level of the output must be equal to .

65. The CS stage of Fig. 7.87 incorporates a degenerated PMOS current source. The degener-

ation must raise the output impedance of the current source to about such that the

voltage gain remains nearly equal to the intrinsic gain of . Assume for both

(4.1) Se ignorarmos a modulacao de comprimentode canal do transistor e se o capacitor CS cumprirdevidamente o seu papel, entao o ganho do am-plificador depende apenas da transcondutancia deM1 e de RD.(4.2) Definido um valor para a corrente de pola-rizacao e para a fonte de alimentacao, o modo deoperacao do transistor (saturacao ou triodo) de-pende apenas de RD.(4.3) O valor da corrente de polarizacao dependede RS , mas nao depende de R1 nem de RD, desdeque o transistor permaneca saturado.(4.4) A impedancia de entrada do amplificador einfinita, uma vez que a corrente de gate do transis-tor e nula. Essa e a grande vantagem do transistorMOS em relacao ao bipolar.(4.5) Os capacitores C1 e CS sao chamados decapacitores de acoplamento, cuja funcao e evitarque as impedancias dos estagios de entrada e sadado amplificador interfiram no ponto de polarizacaodo circuito.

5. Considere o circuito a seguir.(5.1) No caso de o amp-op ter ganho infinito, aentrada inversora e um terra virtual, ja que as cor-rentes de entrada do amp-op sao nulas. No caso de

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 413 (1)

Sec. 8.6 Chapter Summary 413

31. The op amp in Fig. 8.54 suffers from a finite gain. Calculate in terms of and .

32. Due to a manufacturing error, a parasitic resistance has appeared in the adder of Fig.

8.55. Calculate in terms of and for and . (Note that canR

RX

2

outV

F

R1

V1V2 A0

RP

Figure 8.55

also represent the input impedance of the op amp.)

33. The voltage adder of Fig. 8.54 employs an op amp having a finite output impedance, .

Using the op amp model depicted in Fig. 8.44, compute in terms of and .

34. Consider the voltage adder illustrated in Fig. 8.56, where is a parasitic resistance and theR

RX

2

outV

F

R1

V1V2 A0

RP

Figure 8.56

op amp exhibits a finite input impedance. With the aid of the op amp model shown in Fig.

8.43, determine in terms of and .

35. Plot the current flowing through in the precision rectifier of Fig. 8.22(b) as a function of

time for a sinusoidal input.

36. Plot the current flowing through in the precision rectifier of Fig. 8.23(a) as a function of

time for a sinusoidal input.

37. Figure 8.57 shows a precision rectifier producing negative cycles. Plot , , and the

R1

XY

Vout

inV

D1

Figure 8.57

current flowing through as a function of time for a sinusoidal input.

38. Consider the precision rectifier depicted in Fig. 8.58, where a parasitic resistor has ap-

peared in parallel with . Plot and as a function of time in response to a sinusoidal

input. Use a constant-voltage model for the diode.

39. We wish to improve the speed of the rectifier shown in Fig. 8.22(b) by connecting a diode

from node to ground. Explain how this can be accomplished.

40. Suppose in Fig. 8.24 varies from V to V. Sketch and as a function of

if the op amp is ideal.

o amp-op ter ganho finito, a entrada inversora naoe um terra virtual, ja que as correntes de entradado amp-op nao mais sao nulas.(5.2) Como a entrada nao-inversora esta aterrada,a entrada inversora e um terra virtual, indepen-dentemente de o ganho do amp-op ser finito ouinfinito.(5.3) No caso de o amp-op ter ganho finitoA0, a sada do circuito e Vout = (v1/R2 +v2/R1)[RF ||A0(R1||R2||RF ||RP )].(5.4) Considerando o ganho do amp-op infinito,a sada do circuito e Vout = RF [v1/(R2||Rp) +v2/(R1||Rp)]. Basta obter o equivalente deThevenin para cada sinal de entrada e entao usaro teorema da sobreposicao junto com a expressaoconhecida da configuracao inversora.

6. Considere o amplificador a seguir.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 696 (1)

696 Chap. 13 Output Stages and Power Amplifiers

Q1

inV

Q

RL

VCC

VEE

2

1D

D2outV

Q3

Q

Vb1

Vb2 4

Q1

Q

RL

VCC

VEE

2

1D

D2outV

Q3

Q

Vb1

4Vin

(a) (b)

Figure 13.15 (a) Push-pull stage with realization of current sources, (b) stage with input applied to base

of .

circuit can be reduced to that shown in Fig. 13.16(a), revealing a striking resemblance to a current

Q1

VCC

1D

Q3Vb1

(b)

Q1

VCC

Q3Vb1

1D

(a)

Figure 13.16 (a) Simplified diagram of a push-pull stage, (b) illustration of current mirror action.

mirror. In fact, since

(13.15)

where the base current of is neglected and denotes the saturation current of , and

since , we have

(13.16)

To establish a well-defined value for , diode is typically realized as a diode-

connected bipolar transistor [Fig. 13.16(b)] in integrated circuits. Note a similar analysis can be

applied to the bottom half of the circuit, namely, , , and .

The second question can be answered with the aid of the simplified circuit shown in Fig.

13.17(a), where and represents the total small-signal resistance of and . Let

us assume for simplicity that is relatively small and , further reducing the circuit to

(6.1) As correntes de polarizacao de Q3 e Q1 se-guem aproximadamente a mesma proporcao entreas correntes de saturacao reversa de D1 e Q1.(6.2) Em regime senoidal, a eficiencia desse ampli-ficador cresce a` medida que aumentamos a tensaode pico da carga.(6.3) Para que o sistema opere adequadamente, acorrente de polarizacao de Q3 deve ser pelo me-nos igual ao valor maximo da corrente na cargadividido por 1+1, e a corrente de polarizacao deQ4 deve ser pelo menos igual ao modulo do valormnimo da corrente na carga dividido por 2 + 1.(6.4) A aplicacao da entrada entre os diodos e nao logo acima de D1 ou logo abaixo de D2 reduz a distorcao na sada.

A6CB06DF-F9A3-4425-AD23-57A074D91984: 7A2ECF1F-ADC6-419E-BBB9-0A941D0A844A: