Teoremas de Análise - 880E53CCd01

8/18/2019 Teoremas de Análise - 880E53CCd01

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UEL - UNIVERSIDADE ESTADUAL DE LONDRINADEP. ENGENHARIA ELÉTRICA – CTU2ELE024 – LABORATÓRIO DE MEDIDAS ELÉTRICASPROF. Jos A!"#$%&'" &" F'$%($

AULA #2 – Laboratório de Introdução à Med. Elétricas

1. Experimento 1 – Teorema da Superposição

1.1. Introdução

A análise de um circuito com mais de uma fonte de corrente ou de tensão pode ficar bastantecomplexa, principalmente se tal circuito contiver um número excessivo de nós. Felizmente, em umcircuito composto apenas de componentes lineares, o teorema da superposição pode ser aplicadopara simplificar o problema.

Teorema da Superposição: Em um circuito elétrico que contém apenas componentes lineares ecom diversas fontes de corrente e/ou tensão, a tensão e a corrente totais em um determinado ramo éa soma das contribuições individuais de cada fonte de tensão e de corrente. Além disso, para calculara contribuição individual de uma determinada fonte, em um ramo específico, deve-se substituir todasas outras fontes de tensão por curto-circuitos e abrir os terminais de todas as outras fontes decorrente.

Neste experimento, aplicaremos o teorema da superposição a solução de um circuito conversor DAde ! bits e comprovaremos o seu resultado na prática.

1.2. Prearação do E!eri"ento

No circuito da figura abaixo, cada entrada, V 0, V 1 e V 2, pode ser igual a zero ou a 5V.

Prove que a tensão Vout, sobre o resistor R figura abaixo!, " igual a

onde b2, b1 e b0 pode# ser 0 ou 1.

"


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UEL - UNIVERSIDADE ESTADUAL DE LONDRINADEP. ENGENHARIA ELÉTRICA – CTU2ELE024 – LABORATÓRIO DE MEDIDAS ELÉTRICASPROF. Jos A!"#$%&'" &" F'$%($

1.. Monta$e" E!eri"ental

#onte o circuito da fi$ura anterior e preenc%a a tabela a se$uir.

b2 b1 b0 Valor Esperado Valor Real Erro (%)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

A$ora, com o circuito inte$rado &'()*!, $ere a se+-ncia binária da tabela anteriore visualize o resultado no osciloscópio.

1.% &elatório

a! $presente a dedu%ão da equa%ão da tensão Vout na sa&da conversor '($ )*2).

b! $presente a tabela anterior preenc+ida. bserve a teoria de n-#eros significativos

discutida na aula anterior.!

c! sboce a #ontage# realizada co# o conversor '($ e o circuito integrado /34.

xplique a #ontage# co# o /34.!

d! $presente o esbo%o da for#a de onda visualizada e# laboratrio.

e! 6ual a tensão de ali#enta%ão do /34 e qual o valor de tensão na sa&da dos seus

pinos7


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TLF6533

D M 5 4 9 0 D M

7 4 9 0 A D M 7 4 9 3 A

D e c a d e a n d

B i n a r y C o u n t e r s

July 1992

DM5490DM7490A DM7493A

Decade and Binary CountersGeneral DescriptionEach of these monolithic counters contains four master-

slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the

count cycle length is divide-by-five for the 90A and divide-by-eight for the 93A

All of these counters have a gated zero reset and the 90Aalso has gated set-to-nine inputs for use in BCD nine’s com-

plement applications

To use their maximum count length (decade or four-bit bina-ry) the B input is connected to the QA output The input

count pulses are applied to input A and the outputs are as

described in the appropriate truth table A symmetrical di-

vide-by-ten count can be obtained from the 90A counters byconnecting the QD output to the A input and applying the

input count to the B input which gives a divide-by-ten squarewave at output QA

FeaturesY Typical power dissipation

90A 145 mW 93A 130 mW

Y Count frequency 42 MHz

Connection Diagrams

Dual-In-Line Package

TLF6533–1

Order Number DM5490J DM5490W or DM7490AN

See NS Package Number J14A N14A or W14B

Dual-In-Line Package

TLF6533–2

Order Number DM7493ANSee NS Package Number N14A

C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A


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Absolute Maximum Ratings (Note)If MilitaryAerospace specified devices are requiredplease contact the National Semiconductor SalesOfficeDistributors for availability and specifications

Supply Voltage 7V

Input Voltage 55V

Operating Free Air Temperature Range

DM54 b55C to a125CDM74 0C to a70C

Storage Temperature Range b65C to a150C

Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The

parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings

The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation

Recommended Operating Conditions

Symbol Parameter DM5490 DM7490A

UnitsMin Nom Max Min Nom Max

VCC Supply Voltage 45 5 55 475 5 5 25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 08 08 V

IOH High Level Output Current b08 b08 mA

IOL Low Level Output Current 16 16 mA

fCLK Clock Frequency A 0 32 0 32 MHz(Note 5)

B 0 16 0 16

tW Pulse Width A 15 15(Note 5)

B 30 30 ns

Reset 15 15

tREL Reset Release Time (Note 5) 25 25 ns

TA Free Air Operating Temperature b55 125 0 70 C

’90A Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ

Max Units(Note 1)

VI Input Clamp Voltage VCC e Min II e b12 mA b15 V

VOH High Level Output VCC e Min IOH e Max 24 34 VVoltage VIL e Max VIH e Min

VOL Low Level Output VCC e Min IOL e Max 02 04 VVoltage VIH e Min VIL e Max (Note 4)

II Input Current Max VCC e Max VI e 55V 1 mAInput Voltage

IIH High Level Input VCC e Max A 80Current VI e 27V Reset 40 mA

B 120

IIL Low Level Input VCC e Max A b32

Current VI e 04V Reset b16 mA

B b48

IOS Short Circuit VCC e Max DM54 b20 b57 mAOutput Current (Note 2)

DM74 b18 b57

ICC Supply Current VCC e Max (Note 3) 29 42 mA

Note 1 All typicals are at VCC e 5V TA e 25CNote 2 Not more than one output should be shorted at a time

Note 3 ICC is measured with all outputs open both RO inputs grounded following momentary connection to 45V and all other inputs grounded

Note 4 QA outputs are tested at IOL e Max plus the limit value of IIL for the B input This permits driving the B input while maintaining full fan-out capability

Note 5 TA e 25C and VCC e 5V

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’90A Switching Characteristicsat VCC e 5V and TA e 25C (See Section 1 for Test Waveforms and Output Load)

From (Input) RL e 400X

Symbol ParameterTo (Output)

CL e 15 pF Units

Min Max

fMAX Maximum Clock A to QA 32 MHz

Frequency B to QB 16

tPLH Propagation Delay Time A to QA 16 nsLow to High Level Output

tPHL Propagation Delay Time A to QA 18 nsHigh to Low Level Output

tPLH Propagation Delay Time A to QD 48 nsLow to High Level Output

tPHL Propagation Delay Time A to QD 50 nsHigh to Low Level Output

tPLH Propagation Delay Time B to QB 16 nsLow to High Level Output

tPHL Propagation Delay Time B to QB 21 nsHigh to Low Level Output

tPLH Propagation Delay Time B to QC 32 nsLow to High Level Output

tPHL Propagation Delay Time B to QC 35 nsHigh to Low Level Output

tPLH Propagation Delay Time B to QD 32 nsLow to High Level Output

tPHL Propagation Delay Time B to QD 35 nsHigh to Low Level Output

tPLH Propagation Delay Time SET-9 to 30 nsLow to High Level Output QA QD

tPHL Propagation Delay Time SET-9 to 40 nsHigh to Low Level Output QB QC

tPHL Propagation Delay Time SET-0 40 nsHigh to Low Level Output Any Q

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Recommended Operating Conditions

Symbol Parameter DM7493A

UnitsMin Nom Max

VCC Supply Voltage 475 5 525 V

VIH High Level Input Voltage 2 V

VIL

Low Level Input Voltage 08 V

IOH High Level Output Current b08 mA

IOL Low Level Output Current 16 mA

fCLK Clock Frequency A 0 32 MHz(Note 5)

B 0 16

tW Pulse Width A 15(Note 5)

B 30 ns

Reset 15

tREL Reset Release Time (Note 5) 25 ns

TA Free Air Operating Temperature 0 70 C

’93A Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ

Max Units(Note 1)

VI Input Clamp Voltage VCC e Min II e b12 mA b15 V

VOH High Level Output VCC e Min IOH e Max 24 34 VVoltage VIL e Max VIH e Min

VOL Low Level Output VCC e Min IOL e Max 02 04 VVoltage VIH e Min VIL e Max (Note 4)

II Input Current Max VCC e Max VI e 55V 1 mAInput Voltage

IIH High Level Input VCC e Max Reset 40Current VI e 24V A 80 mA

B 80

IIL Low Level Input VCC e Max Reset b16Current VI e 04V

A b

32 mAB b32

IOS Short Circuit VCC e Max b18 b57 mAOutput Current (Note 2)

ICC Supply Current VCC e Max (Note 3) 26 39 mA

Note 1 All typicals are at VCC e 5V TA e 25C

Note 2 Not more than one output should be shorted at a time

Note 3 ICC is measured with all outputs open both R0 inputs grounded following momentary connection to 45V and all other inputs grounded

Note 4 QA outputs are tested at IOL e Max plus the limit value of IIL for the B input This permits driving the B input while maintaining full fan-out capability

Note 5 TA e 25C and VCC e 5V

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’93A Switching Characteristicsat VCC e 5V and TA e 25C (See Section 1 for Test Waveforms and Output Load)

From (Input) RL e 400X

Symbol ParameterTo (Output)

CL e 15 pF Units

Min Max

fMAX Maximum Clock A to QA 32 MHz

Frequency B to QB 16

tPLH Propagation Delay Time A to 16 nsLow to High Level Output QA

tPHL Propagation Delay Time A to 18 nsHigh to Low Level Output QA

tPLH Propagation Delay Time A to 70 nsLow to High Level Output QD

tPHL Propagation Delay Time A to 70 nsHigh to Low Level Output QD

tPLH Propagation Delay Time B to 16 nsLow to High Level Output QB

tPHL Propagation Delay Time B to 21 nsHigh to Low Level Output QB

tPLH Propagation Delay Time B to 32 nsLow to High Level Output Q

CtPHL Propagation Delay Time B to 35 ns

High to Low Level Output QC

tPLH Propagation Delay Time B to 51 nsLow to High Level Output QD

tPHL Propagation Delay Time B to 51 nsHigh to Low Level Output QD

tPHL Propagation Delay Time SET-0High to Low Level Output to 40 ns

Any Q

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Function Tables (Note D)

90A

BCD Count Sequence(See Note A)

Count Outputs

QD

QC

QB

QA

0 L L L L1 L L L H

2 L L H L3 L L H H4 L H L L

5 L H L H6 L H H L

7 L H H H8 H L L L9 H L L H

90ABCD Bi-Quinary (5-2)

(See Note B)

Count Outputs

QA

QD

QC

QB

0 L L L L1 L L L H


5 H L L L6 H L L H

7 H L H L8 H L H H9 H H L L

93ACount Sequence

(See Note C)

Count Outputs

QD

QC

QB

QA

0 L L L L1 L L L H


5 L H L H6 L H H L

7 L H H H8 H L L L9 H L L H

10 H L H L11 H L H H

12 H H L L13 H H L H

14 H H H L15 H H H H

90A

ResetCount Function Table

Reset Inputs Outputs

R0(1) R0(2) R9(1) R9(2) QD QC QB QA

H H L X L L L LH H X L L L L LX X H H H L L H

X L X L COUNTL X L X COUNT

L X X L COUNTX L L X COUNT

93A

ResetCount Function Table

Reset Inputs Outputs

R0(1) R0(2) QD QC QB QA

H H L L L LL X COUNTX L COUNT

Note A Output QA is connected to input B for BCD count

Note B Output QD is connected to input A for bi-quinary count

Note C Output QA is connected to input B

Note D H e High Level L e Low Level X e Don’t Care

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Logic Diagrams

90A

TLF6533–3

93A

TLF6533–4

The J and K inputs shown without connection are for reference only and are functionally at a high level

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Physical Dimensions inches (millimeters)

14-Lead Ceramic Dual-In-Line Package (J)

Order Number DM5490JNS Package Number J14A

14-Lead Molded Dual-In-Line Package (N)Order Number DM7490AN or DM7493AN

NS Package Number N14A

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D M 5 4 9 0 D M 7 4 9 0 A

D M 7 4 9 3 A

D e c a d e a n d B i n a r y C o u n t e r s

Physical Dimensions inches (millimeters) (Continued)

14-Lead Ceramic Flat Package (W)

Order Number DM5490WNS Package Number W14B

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONALSEMICONDUCTOR CORPORATION As used herein

1 Life support devices or systems are devices or 2 A critical component is any component of a lifesystems which (a) are intended for surgical implant support device or system whose failure to perform can

into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the lifefailure to perform when properly used in accordance support device or system or to affect its safety or

with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injuryto the user

National Semiconducto r National Semiconduct or Natio nal Semiconducto r National Semiconduct or

Corporation Europe Hong Kong Ltd Japan Ltd1111 West Bardin Road Fax (a4 9) 0 -1 80 -5 30 8 5 8 6 1 3t h F lo or S tr ai gh t B lo ck T el 8 1- 04 3- 29 9- 23 09Arlington TX 76017 Email cnjwget ev m2 n sc c om O ce an C en tr e 5 C an to n R d F ax 8 1- 04 3- 29 9- 24 08Tel 1(800) 272-9959 Deutsch Tel (a49) 0-180-530 85 85 Tsimshatsui KowloonFax 1(800) 737-7018 Eng lish Tel (a49 ) 0- 180 -53 2 7 8 32 Ho ng K ong

Franais Tel (a4 9) 0 -1 80 -5 32 9 3 5 8 T el ( 85 2) 2 73 7- 16 00Italiano Tel (a4 9) 0 -1 80 -5 34 1 6 8 0 F ax ( 85 2) 2 73 6- 99 60

National doesnot assumeany responsibilityfor useof anycircuitry described nocircuit patent licenses areimplied and National reserves the right at anytime without noticeto changesaid circuitryand specifications

Teoremas de Análise - 880E53CCd01

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