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Verilog-A:An Introduction
for Compact Modelers
Geoffrey Coram
MOS-AK/ESSDERC/ESSCIRC Workshop (Montreux 2006)
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Outline
The ProblemModeling Languages
Diode Example
GuidelinesAdmonishments
Compiler Optimizations
ConclusionReferences (and Further Examples)
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M
odelingIn
terface
The Solution
SpectreEldo
ADSSmash
Nanosim
HSIM
APLAC
AMSGolden
Gate
HSPICE
VBIC
HiCUMBSIM
Mextram
ACM
HiSIM
USIM
PSP
MM20
HVEKV
from McAndrew, BMAS 2003
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Modeling Languages
Programming languages:FORTRAN (SPICE2)C (SPICE3)+ Fast, direct access to simulator
Must compute derivatives No standard interface Intimate knowledge of simulator required
MATLAB+ Excellent for data fitting Does not run directly in any analog simulator
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Behavioral Modeling Languages
Verilog-A Verilog-AMSPushed by Cadence, came to market earlierVerilog-A from Open Verilog International became part
of Accellera Verilog-AMS
IEEE 1800 authorized to develop SystemVerilog-AMS
Verilog-AMS runs in the same AMS simulators asVHDL-AMS
+ Verilog-A runs in Spectre, HSpice, ADS, Eldoand internal simulators of semiconductor companies
+Clear definition of A+ Verilog-AMS LRM 2.2 was driven by the requirements
for compact modeling
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V-AMS LRM 2.2 Additions
Highlights for compact modeling:output / operating point parametersvdsat, id_chan
also gm, cgs using new ddx() operator
$simparam to access simulator quantities(gmin)
$param_given
paramsets replace and extend Spice .modelcards
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VHDL-AMS Diode
-- Modified from http://www.syssim.ecs.soton.ac.uk/vhdl-ams/examples/smpr.htm
library IEEE;use IEEE.math_real.all;use IEEE.electrical_systems.all;use IEEE.FUNDAMENTAL_CONSTANTS.all;
entity diode is
generic (Isat: current := 1.0e-14); -- Saturation current [Amps]port (terminal p, n : electrical);
endentity diode;
architecture ideal of diode isquantity v across i through p to n;
constant TempC : real := 27.0; -- Ambient Temperature [Degrees]constant vt : real := PHYS_K*(273.15 + TempC )/PHYS_Q; -- Thermal Voltagebegin
i == Isat*(limit_exp(v/vt) - 1.0);endarchitecture ideal;
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VHDL-AMS Diode
-- Modified from http://www.syssim.ecs.soton.ac.uk/vhdl-ams/examples/smpr.htm
library IEEE;use IEEE.math_real.all;use IEEE.electrical_systems.all;use IEEE.FUNDAMENTAL_CONSTANTS.all;
entity diode is
generic (Isat: current := 1.0e-14); -- Saturation current [Amps]port (terminal p, n : electrical);
endentity diode;
architecture ideal of diode isquantity v across i through p to n;
constant TempC : real := 27.0; -- Ambient Temperature [Degrees]constant vt : real := PHYS_K*(273.15 + TempC )/PHYS_Q; -- Thermal Voltagebegin
i == Isat*(limit_exp(v/vt) - 1.0);endarchitecture ideal;
isis a keyword!
TempC is a constant!
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Verilog-A Diode
`include "disciplines.vams"module diode(a,c);
inout a,c; electrical a,c;parameter real is = 10p from (0:inf);
real id;(*desc = "conductance "*) real gd;analogbegin
id = is * (limexp(V(a,c) / $vt) 1.0);
gd = ddx(id, V(a));I(a,c)
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Verilog-A Diode
`include "disciplines.vams"module diode(a,c);
inout a,c; electrical a,c;parameter real is = 10p from (0:inf);
real id;(*desc = "conductance "*) real gd;analogbegin
id = is * (limexp(V(a,c) / $vt) 1.0);
gd = ddx(id, V(a));I(a,c)
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Verilog-A Diode
`include "disciplines.vams"module diode(a,c);
inout a,c; electrical a,c;parameter real is = 10p from (0:inf);
real id;(*desc = "conductance "*) real gd;analogbegin
id = is * (limexp(V(a,c) / $vt) 1.0);
gd = ddx(id, V(a));I(a,c)
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Verilog-A Diode
`include "disciplines.vams"module diode(a,c);
inout a,c; electrical a,c;parameter real is = 10p from (0:inf);
real id;(*desc = "conductance "*) real gd;analogbegin
id = is * (limexp(V(a,c) / $vt) 1.0);
gd = ddx(id, V(a));I(a,c)
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Verilog-A Diode
`include "disciplines.vams"module diode(a,c);
inout a,c; electrical a,c;parameter real is = 10p from (0:inf);
real id;(*desc = "conductance "*) real gd;analogbegin
id = is * (limexp(V(a,c) / $vt) 1.0);
gd = ddx(id, V(a));I(a,c)
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Verilog-A Diode
`include "disciplines.vams"module diode(a,c);
inout a,c; electrical a,c;parameter real is = 10p from (0:inf);
real id;(*desc = "conductance "*) real gd;analogbegin
id = is * (limexp(V(a,c) / $vt) 1.0);
gd = ddx(id, V(a));I(a,c)
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Verilog-A Jump Start
Looks much like CIntuitive and easy to read and learn
Start with an existing model and modify
Based on through and across variablesSet up is for KCL and KVL
Understand the contribution operatorI(di,si)
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Best Practices
Models formulated in currents I(V) andcharges Q(V)most natural for modified nodal analysis (MNA)
Q(V) not C(V) to ensure conservation of chargeddt(Q(V)) != ddt(C(V) * V) != C(V) * ddt(V)
No access to previous timestepswatch non-quasi-static formulations
allows model to run in RF simulatorNoises as current sources
No discontinuities
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Discontinuities
Spice requires continuous derivativesConsider this code:
if (vbs == 0.0)begin
qbs = 0.0;capbs = czbs+czbssw+czbsswg;
endelseif (vbs < 0.0)begin
qbs =
I(b,s)
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Discontinuities
Resulting C code:if (vbs == 0.0) {qbs = 0.0;
dqbs_dvbs = 0.0;//capbs=czbs+czbssw+czbsswg;
}elseif (vbs < 0.0) {
qbs =
Automatic derivativediffers from
intended value
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Discontinuities
HiSIM2 Verilog-A(beta code)
Clipping in C codemay affect values
and derivativesdifferently
HiSIM Verilog-A (beta code)ac drain current (real part)
hisim ir(m1,d)
0
.5
1
1.5
2
2.5
3
3.5
4
x1e-3
-80 -40 0 40 80 120 160 200vd, x1e-3
if ( Vds
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Compiler Optimizations
Common subexpressionsid = is * (exp(vd/vtm) 1.0);gd = is/vtm * exp(vd/vtm);
Eliminating internal nodesif (rs == 0.0)
V(b_res)
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analysis()
Consider this code:
if (analysis("tran"))begin
qd =
No capacitance in:
small-signal ac analysis,harmonic balance, envelope following
Pseudo-transient homotopy
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analysis()
Consider this code:if (analysis("noise"))begin
flicker =strongInversionNoiseEval(vds,temp);
Compiler/Simulator MUST do this optimization
But what about PNOISE, HBNoise, ?
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Events
Consider this code:@(initial_step)beginisdrain = jsat * ad;
What happens for a dc sweep?dont want re-computing for bias sweep
need re-computing for temperature sweep
Even for transient,initial_stepis true for every iteration at time=0
Compiler/Simulator MUST do this optimization
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ADMS Magic Names
ADMS uses special block names toidentify sections of code
Eg PSP Verilog-A:
begin : initializeModel
NSUB0_i = `CLIP_LOW(NSUB0,1e20);
//
Doesnt hurt for other compilers
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Software Practices
Use consistent indentationAlign code vertically on =
Use meaningful namesuse maximum size (8) to help vertical alignment
Include comments: brief description,reference documentation
Physical constants are notdated and
could changemodel results would then change
define physical constants for a model
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PSP Model Code
// 4.2.4 Surface potential at source side
Gf2 = Gn2 * f_s;inv_Gf2 = 1.0 / Gf2;
Gf = sqrt(Gf2);
xi = 1.0 + Gf * `invSqrt2;
inv_xi = 1.0 / xi;
Ux = Vsbstar * inv_phit1;
xn_s = phib * inv_phit1 + Ux;
if (xn_s < `se)
delta_ns = exp(-xn_s) * inv_f;
else
delta_ns = `ke * inv_f / `P3(xn_s - `se);
margin = 1e-5 * xi;
`sp_s(x_s, xg, xn_s, delta_ns)
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PSP Model Code
// 4.2.4 Surface potential at source side
Gf2 = Gn2 * f_s;inv_Gf2 = 1.0 / Gf2;
Gf = sqrt(Gf2);
xi = 1.0 + Gf *
inv_xi = 1.0 / xi;
Ux = Vsbstar * inv_phit1;
xn_s = phib * inv_phit1 + Ux;
if (xn_s < `se)
delta_ns = exp(-xn_s) * inv_f;
else
delta_ns = `ke * inv_f / `P3(xn_s - `se);
margin = 1e-5 * xi;
`sp_s(x_s, xg, xn_s, delta_ns)
equation number fromdocumentationand explanation
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PSP Model Code
// 4.2.4 Surface potential at source side
Gf2 = Gn2 * f_s;inv_Gf2 = 1.0 / Gf2;
Gf = sqrt(Gf2);
xi = 1.0 + Gf * `invSqrt2;
inv_xi = 1.0 / xi;
Ux = Vsbstar * inv_phit1;
xn_s = phib * inv_phit1 + Ux;
if (xn_s < `se)
delta_ns = exp(-xn_s) * inv_f;
else
delta_ns = `ke * inv_f / `P3(xn_s - `se);
margin = 1e-5 * xi;
`sp_s(x_s, xg, xn_s, delta_ns)
alignment forreadability
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PSP Model Code
// 4.2.4 Surface potential at source side
Gf2 = Gn2 * f_s;inv_Gf2 = 1.0 / Gf2;
Gf = sqrt(Gf2);
xi = 1.0 + Gf * `invSqrt2;
inv_xi = 1.0 / xi;
Ux = Vsbstar * inv_phit1;
xn_s = phib * inv_phit1 + Ux;
if (xn_s < `se)
delta_ns = exp(-xn_s) * inv_f;
else
delta_ns = `ke * inv_f / `P3(xn_s - `se);
margin = 1e-5 * xi;
`sp_s(x_s, xg, xn_s, delta_ns)
indentationof blocks
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Other Model Code
//----Self Heating Effect
//(implemented only on mobility)------PD = (VDE-VS)*Id;if (SH_switch ==1) begin
I(TH)
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Other Model Code
//----Self Heating Effect
//(implemented only on mobility)------PD = (VDE-VS)*Id;if (SH_switch ==1) begin
I(TH)
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Other Model Code
// new model for mobility reduction,
//linked to the charges model// !! mb 98/10/11 (r10) introduced fabs(Eeff)(jpm) //
if ((qb + eta_qi*qi) > 0.0) begin
E0_Q_1 = 1.0 + T0*(qb + eta_qi*qi); endelse begin
E0_Q_1 = 1.0 - T0*(qb + eta_qi*qi); end
T0_GAMMA_1 = 1.0 + T0*GAMMA_sqrt_PHI;
// !! mb 97/06/02 ekv v2.6beta = KP_Weff * T0_GAMMA_1 / (Leq * E0_Q_1+1e-60);
// !! mb 97/07/18
cryptic comments where is Eeff??
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Coding Style
Verilog-A can be very readable
Characterization engineers andsimulator people will read it
Make a good impression!
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Conclusion
Verilog-A is a powerful and easy-to-usecompact modeling language
Writing a good compact model stillrequires care and rigor
Many examples now available
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References
Designers Guidehttp://www.designers-guide.org/
Forum
Verilog-A model library (VBIC, MOS11, JFET, etc.)
MCAST (Prof. CJ Richard Shi)http://www.ee.washington.edu/research/
mscad/shi/mcast.htmlAutomatic compiler beats hand-coded C
http://www.designers-guide.org/http://www.ee.washington.edu/research/mscad/shi/mcast.htmlhttp://www.ee.washington.edu/research/mscad/shi/mcast.htmlhttp://www.ee.washington.edu/research/mscad/shi/mcast.htmlhttp://www.ee.washington.edu/research/mscad/shi/mcast.htmlhttp://www.designers-guide.org/http://www.designers-guide.org/http://www.designers-guide.org/7/31/2019 06 Coram Mos-Ak06
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Examples
Verilog-A model library athttp://www.designers-guide.org/VerilogAMS/ VBIC, MOS11, JFET, etc.
Silvaco public domain models (non-commercial use)https://src.silvaco.com/ResourceCenter/en/downloads/verilogA.jspBSIM3, BSIM4, BJT, etc.
But: watch out for @(initial_step)!
PSP http://pspmodel.asu.edu/
Mextram http://hitec.ewi.tudelft.nl/mug/
HiCUM http://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html
http://www.designers-guide.org/VerilogAMS/https://src.silvaco.com/ResourceCenter/en/downloads/verilogA.jsphttps://src.silvaco.com/ResourceCenter/en/downloads/verilogA.jsphttp://pspmodel.asu.edu/http://hitec.ewi.tudelft.nl/mug/http://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.htmlhttp://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.htmlhttp://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.htmlhttp://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.htmlhttp://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.htmlhttp://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.htmlhttp://hitec.ewi.tudelft.nl/mug/http://pspmodel.asu.edu/https://src.silvaco.com/ResourceCenter/en/downloads/verilogA.jsphttps://src.silvaco.com/ResourceCenter/en/downloads/verilogA.jsphttp://www.designers-guide.org/VerilogAMS/http://www.designers-guide.org/VerilogAMS/http://www.designers-guide.org/VerilogAMS/Top Related