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Datapath Design 1
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Building the Datapath
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Datapath Design 2
Definitions• The processor executes instructions that operate
on data.• Data is modified, moved, produced and
discarded as a result of the program’s target• The Datapath is the hardware circuitry of the
processor where the Data is:– Temporarily stored– Modified
• By opposition, the Control Unit is responsible for controlling and monitoring the Datapath to ensure the proper execution of the instructions
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Datapath Design 3
Digital Circuit Model
CombinationalLogic
Memorization Elements
A Digital Circuit is modeled as a Sequential Circuit
It consists of several Memorization Elements connected to one another through combinational logic blocks. • The Memorization Elements are governed by clocking signals defined
by a clocking methodology• Inputs of any combinational logic block come from memorization
elements and are fed-back into memorization elements
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Datapath Design 4
Clocking MethodologyUse an edge-triggered clocking methodology
D
Ck
Q
Ck D Qt+1
↑ 0 0
↑ 1 1
0/1/↓ - Qt
0/1/↓ - Qt
• Memorization elements values are only updated on the active edge of the clock• Memorization elements outputs are available immediately after their update and stable for the whole duration of the clock cycle
CombinationalLogic
Input
Ck
Output
Memorization Element Delay
Combinational Logic Delay
No infinite loop using edge-triggered Memorization Elements
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Datapath Design 5
General Design Methodology
• Clearly understand the list of requirements• Translate the requirements list into design-oriented
requirements that can be directly mapped into design blocks• Divide the design into several design blocks organized by
function that implement the list of requirements• Clearly define the inputs and outputs of each block (interface)• Connect the blocks together to form the design entity as a
whole• Refine the details by verifying that each item in the
requirement list is fully fulfilled. Add the necessary modifications if needed.
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Datapath Design 6
Requirements• To simplify the design, only a subset of the MIPS
instruction set is to be supported by the datapath. The subset consists of the following instructions:– Arithmetic and Logic instructions
• Add, Sub, And, Or and Slt– Both Register and Immediate addressing modes are included
– Memory Access Instructions• Lw and Sw
– Control Sequence instructions:• branch if equal (Beq)
• Start with a simple implementation that uses a single clock cycle for every instruction
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Computer Engineering Department
Computer Engineering Department
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Datapath Design 7
Single Clock Cycle Model
CombinationalLogic
StateElement
In a single clock cycle execution model:• Every instruction is executed in a single clock cycle• The state elements are modified at the end of the execution of each
instruction. Means:– Datapath architecture should not have intermediate registers to store partial
results in the middle of the execution of one instruction
Instruction Flow
Ck
Instruction i-1 Instruction i Instruction i+1 Instruction i+2
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Datapath Design 8
How to Proceed
Need to implement a Datapath that executes 3 types of instructions:• Arithmetic and Logic Instructions• Memory Access Instructions• Control of Sequence Instructions
Solution: Use Incremental Design Methodology
Difficult to address all the 3 instruction type details and specificities at the same time
Start with a Datapath that can execute Arithmetic and Logic Instructions Alone
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Computer Engineering Department
College of ComputerScience And Engineering
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Datapath Design 9
A/L Instruction Properties
• The processor executes the Arithmetic and Logic Instructions as follows:– Fetch the instruction from Memory– Fetch its operands. Operands are either
• Both registers: R-type• One operand is a register and the other is an immediate
value– Execute the required operation (add, sub, and, or,
slt)– Store the result in the destination register
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Datapath Design 10
Fetching Instructions
The processor fetches the instructions from memory one by one before executing them
The address is usually kept in a register
called PC (Program Counter)
The processor needs to know the address of the instruction to be able to fetch it
The PC is the first State Element
The PC is incremented to point to the next instruction in memory
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Datapath Design 11
PC Block
– Non-clocked memory (treated as a combinational circuit) satisfies the single cycle execution requirement
• The PC contains the address of the next instruction to be executed.
• For simplicity, we assume that the instruction and data memories are separate entities.
• The instruction address (PC register output) is fed into the memory to fetch the instruction from the instruction memory
• Question: Is the instruction memory a combinational or sequential block?– Clocked memory (synchronous) requires min. two clock cycles: 1st to read the instruction from the
memory and 2nd to execute the instruction. Conflict with single cycle execution requirement
PC
Addr
Instruction
Ck
R/Wb
Dout
Din
• Instruction Memory is read only. No need for R/Wb signal and Din bus.
Iout
• Instructions are in memory
Memory
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Datapath Design 12
Register File• MIPS contains 32 registers. Need a Register File• First support A/L Instructions of R-type. Need 2 Read and 1 Write operation per instruction
– Option 1: 1 Read/Write Port. Cannot perform 2 reads and 1 write in a single clock cycle– Option 2: 1 Read Port and 1 Read/Write Port. Cannot perform 1 read and 1 write during one clock cycle
– Option 3: 2 Read Ports and 1 Write Port. Read ports are asynchronous and Write port is clocked
Read Register 1
Read Register 2
Write Register
Write Data
ReadData 1
ReadData 2
RegisterFile
5
5
5
32
32
32ComingFrom
Instruction
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Datapath Design 13
Instruction Register ?Do we need an Instruction Register to save
the Fetched Instruction?
No, because:• Instruction Memory is asynchronous• AND Single-cycle execution datapath• AND PC is modified after the current instruction
execution is finished
PC
Ck
Iout
PC out
Delay
Instruction
Memory
Delay
No Instruction Register means:Use Output of Instruction Memory as
Instruction Register
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Datapath Design 14
Connecting the Register File
R-type instruction format
PC
Addr
Instruction
Iout
Memory
op functrs rt rd shamt
For R-type A/L instructions, connect the Rs, Rt and Rd fields of the instruction to the register address input of the register file.
Bits: 31 26 25 21 20 16 15 11 10 6 5 0
• Connect Rs Field to Read Port Address 1
• Connect Rt Field to Read Port Address 2
• Connect Rd Field toWrite Port AddressRead Register 1
Read Register 2
Write Register
Write Data
ReadData 1
ReadData 2
RegisterFile
5
5
5
32
32
3232
Rs: I[25:21]
Rt: I[20:16]
Rd: I[15:11]
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Datapath Design 15
Executing The Operation• Use the ALU to perform the Operation.
• Read Register 1 Data is connected to 1st ALU operand
Zero
ALUOp
ALU
• Read Register 2 Data is connected to 2nd ALU operand
• Result is written back in the Register File through the unique Write Port
Read Register 1
Read Register 2
Write Register
Write Data
ReadData 1
ReadData 2
RegisterFile
5
5
5
32
32
32Coming
FromInstruction
RegWrite
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Datapath Design 16
Getting to The Next Instruction
To get to the next instruction we need to:• Increment PC: PC PC + 4 (Addressing space is in bytes, so to get to the
next 32 bits which are 4 bytes, add the value 4)• Wait for the rising edge of the clock
Because we are in a single-cycle execution model, the PC is updated only at the rising edge of the clock which means: We should prepare
the next value of the PC beforehand.
We Need an adder to perform PC + 4. We have two choices:
• Use the ALU:• Add an adder specially dedicated to adding 4 to the
PC.
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Datapath Design 17
Using the ALU to Increment the PC
ALU
Read Register 1
Read Register 2
Write Register
Write Data
ReadData 1
ReadData 2
RegisterFile
4
PC
First Option, connect the two sources PC and Registers directly to the ALU
Bus Conflict
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Datapath Design 18
Using the ALU to Increment the PC (2)
ALU
Read Register 1
Read Register 2
Write Register
Write Data
ReadData 1
ReadData 2
RegisterFile
4
PC
Second Option, connect the two sources PC and Registers through Muxes to select which block uses the ALU
Need 2 phases (clock cycles)
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Datapath Design 19
PC Increment Block
PC
+
4
No choice but to add an adder dedicated for Computing the value: PC + 4
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Datapath Design 20
Datapath for R-type A/L Inst.
PC
+
4
Addr
Instruction
Iout
Memory
Zero
ALU
Read Register 1
Read Register 2
Write Register
Write Data
ReadData 1
ReadData 2
Register Write
RegisterFile
RegWrite
ALUOp
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Datapath Design 21
Support for I-type Instructions
For I-type Instructions, the second operand is an immediate value
I-type instruction format
op rs rd I Field
Bits: 31 26 25 21 20 16 15 0
Second Operand is a signed 16-bits immediate value:• Needs to be extended to 32 bits Sign extend it
– Add Sign Extension Block
• The register destination number comes from the rt field (bits [20:16]) instead of coming from the rd field (bits [15:11])
– Add a Mux to select between the rd and rt field for the register destination number
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Datapath Design 22
I-type Support
Addr Iout
InstructionMemory
Zero
ALU
Read Reg. 1
Read Reg. 2
Write Reg.
Write Data
ReadData 1
ReadData 2
Register Write
Reg.File
Reg. Write
16 32Sign Extend
5
5
5
32Rs: I[25:21]
Rt: I[20:16]
Rd: I[15:11]
I Field: I[15:0]
Sign Extension Block added to sign extend the Immediate value from 16 to 32 bits
ALU Source Mux added to select the second operand between Rs Register and The Sign Extended Immediate Value
Register Destination Mux added to select the register destination number between the Rd field (R-type) and the Rt field (I-type)
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Datapath Design 23
Memory Access InstructionsTwo instructions to access the memory: lw and sw.• Both instructions use the displacement addressing mode where the
address is the result of the addition of a register value to a signed displacement: EA = Rs + disp
• Rs is read from the Register File. So the Address Calculation takes place into the ALU.
• The Address is then used to access the data memory• The Data Memory is a Read/Write Memory.
Addr Dout
DataMemory
Din
• Two Control Signals are required for the Data Memory: MemRead and MemWrite
MemRead
MemWrite
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Datapath Design 24
Load InstructionLw reads a word from the memory and stores it in the Register FileThe Data Memory Read Access is the same as the Instruction Memory Access. It is Asynchronous and behaves like a Combinational Circuit.
The Memory Read Data need to be stored in the Register File. However, Register File Write Data input already connected to output of ALU (for Arithmetic/Logic Instructions)
Solution: Insert a Mux to select between ALU output and Data memory Read Data.
ALU
Read Reg. 1
Read Reg. 2
Write Reg.
Write Data
ReadData 1
ReadData 2
Reg.File
Sign Extend
Addr Dout
DataMemory
Din
Addr Iout
InstructionMemory
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Datapath Design 25
Store InstructionSw writes a register into the memory
Need to Connect the Din Bus of the Data Memory to the Appropriate signal
Addr Iout
InstructionMemory ALU
Read Reg. 1
Read Reg. 2
Write Reg.
Write Data
ReadData 1
ReadData 2
Reg.File
Sign Extend
Addr Dout
DataMemory
Din
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Datapath Design 26
Branch Equal (beq) InstructionBeq rs, rt, label: Branch to “label” if rs == rt.
Means: if rs == rt PC PC + Offset + 4else PC PC + 4
Structural Conflict: Need to1. Compare Rs and Rt2. Compute PC + Offset + 4
• Use the ALU to perform the comparison.• Add a new adder for the displacement.
How to Connect 16-bit Offset to a 32-bit adder?• Beq is I-type. • Offset field is 16-bits signed Sign extend it • Represents a word Offset Shift left by 2 positions
In Summary
• Add New Adder to Compute PC + Offset• Offset is sign-extended left shifted to be 32
bits• ALU is used for comparison
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Datapath Design 27
Branch Equal Instruction (2)
ALU
Read Reg. 1
Read Reg. 2
Write Reg.
Write Data
ReadData 1
ReadData 2
Reg.File
Sign Extend
Addr Dout
DataMemory
Din
LeftShift
PC 4 ++
Mux inserted to select between:• PC + Offset + 4: When it is a
branch instruction and the branch is taken
• PC + 4: in all the other cases
Addr Iout
InstructionMemory
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Datapath Design 28
RegDst
Showing The Control Signals
ALU
Read Reg. 1
Read Reg. 2
Write Reg.
Write Data
ReadData 1
ReadData 2
Reg.File
Sign Extend
Addr Dout
DataMemory
Din
LeftShift
PC 4 ++
Addr Iout
InstructionMemory
ALUOp
RegWrite
ALUSrc MemtoReg MemRead
MemWrite
PCSrc
Zero
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Datapath Design 29
Control SignalsSignal Width (bits) Value Effect
PCSrc 10 Select PC + 4
1 Select PC + Offset + 4
RegDst 10 Register Destination Number is taken from Rd field (bits [15:11])
1 Register Destination Number is taken from Rt field (bits [20:16])
ALUSrc 10 ALU Second Operand is Register
1 ALU Second Operand is Immediate Value
ALUOp 3
000 Add
001 Sub
010 And
011 Or
100 Slt
MemtoReg 10 Select the Output of the ALU to be written in the Register File
1 Select the Read Data from Memory to be written in the Register File
RegWrite 1 1 Enables a Write to the Destination Register’s location
MemWrite 1 1 Initiate a Write to Data Memory
MemRead 1 1 Initiate a Read to Data Memory
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Datapath Design 30
A Word about ALU ControlALU Control, as designed in section 4 has two control signals:• Operation• Binvert
The ALU in all what preceded includes its own control signals generation block that takes the ALUOp control signal and translates it into the Operation and Binvert signals.
ALU
ALUOp
ALUCtrl Gen.
OperationBinvert
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Datapath Design 31
Control Signals SettingsInstruction Type RegDst ALUSrc ALUOp PCSrc MemtoReg RegWrite MemRd MemWr
AddR 0 0 000 0 0 1 0 0
I 1 1 000 0 0 1 0 0
SubR 0 0 001 0 0 1 0 0
I 1 1 001 0 0 1 0 0
AndR 0 0 010 0 0 1 0 0
I 1 1 010 0 0 1 0 0
OrR 0 0 011 0 0 1 0 0
I 1 1 011 0 0 1 0 0
Slt R 0 0 100 0 0 1 0 0
Lw I 1 1 000 0 1 1 1 0
Sw I X 1 000 0 X 0 0 1
Beq I X 0 001 1(*) X 0 0 0
(*) if Zero (from ALU) is equal to 1
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Datapath Design 32
Datapath and Control
RegDst
ALU
Read Reg. 1
Read Reg. 2
Write Reg.
Write Data
ReadData 1
ReadData 2
Reg.File
Sign Extend
Addr Dout
DataMemory
Din
LeftShift
PC 4++
Addr Iout
InstructionMemory
ALUOp
RegWrite
ALUSrc MemtoReg MemRead
MemWriteP
CS
rc
Zero
Control
BranchRegDstRegWriteALUSrcALUOpMemtoRegMemReadMemWriteBranch
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Datapath Design 33
Multicycle Implementation• Multiple clock cycles to execute a single instruction
• Clock cycle is shorter
• No conflict between different operations on block usage. A block can be used by an entity in a clock cycle and reused to do something else in another clock cycle
• Need intermediate registers to save intermediate values
• Optimal implementation: shortest clock cycle time .vs. smallest number of clock cycles per instruction
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Datapath Design 34
How many clock cycles ?Choose a clock cycle to perform ONE operation at a time. For example:
– Instruction Fetch – Operand Fetch– ALU Operation– PC PC + 4– Memory Access– Result Write Back in Register File
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Datapath Design 35
Instruction Fetch• PC Instruction Memory• Read Instruction• Store Instruction into Instruction Register
PC Addr Iout
InstructionMemory
IR IR Introduced to allow PC to change its value without waiting until the last clock cycle of the instruction execution
Since ALU is unused during the Instruction Fetch cycle:Use the ALU to perform PC + 4 and store it back in the PC
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