FPGA Design Flow & SynthesisFPGA Design Flow & Synthesis•™材.pdf · 2015-09-17 ·...

教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟雲林科技大學電子系許明華

FPGA DeviceFPGA DeviceFPGA Device

FPGA Design Flow & SynthesisFPGA Design Flow & SynthesisFPGA Design Flow & Synthesis

DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform

DIP Prototype System Measurement

Design ExampleDesign ExampleDesign Example


IP Prototype System Measurement

•Ball-less Optical Mouse

•System Signal Measurement

•Data Analysis


Ball-less Optical Mouse System


System FeaturesSingle Chip Solution.

800 dpi Resolution

12 in./sec. Maximum Velocity

0.15g Maximum Acceleration

18-pin DIP package

Low Power ConsumptionAuto Power-down Mode and wake up

Operating Voltage VDD 3 3.15V to 3.45 V

VDD 5 4.75V to 5.25 V


Optical Mouse Hardware Module

IP IP

IP or µp+software

Quadrature

I C2

AMBA

Interface


System I/O Definition

I/O No.

Name Type Description I/O No.

Name Type Description

1 XA I/O XA Output 8 OSCI I Oscillator Input

2 XB I/O XB Output 9 GND Ground 3 YB I/O YB Output 10 OSC2 O Oscillator

Output 4 YA I/O YA Output 11 GND I Ground 5 XY_LED O LED

Control Output

12 VDD5 I 5.0 V VDD

6 VDD3 I 3.3 V VDD 13 VDD5 I 5.0 V VDD 7 REFB I Internal

Reference 14 NRESET I NRESET


System SpecificationParameter Symbo

l Min. Typ. Max. Unit Note

Speed 12 In/sec Acceleration 0.15 g Light level onto IC IRRinc 40 25000 MWm

2 λ= 639 nm

LED Peak Wavelength 639 nm Sensor Pitch (both X and Y)

30 um

Output Frame Rate (Normal Mode)

1500 frame

Output Frame Rate (Sleep Mode)

128 frame

Clock Frequency 13.5 18.432 27.0 MHz Power Supply, VDD5 4.75 5.0 5.25 Volt Power Supply, VDD3 3.15 3.3 3.45 Volt Current, Normal Mode

mA

Current, Sleep Mode mA


Ball-less Optical Mouse System

Application Specific Demo Board (Natl. Yunlin Univ.)


ADC IP Image Sensor Input

PowerLED

FPGA I/O Pin

FPGA I/OPin

DIP Sw.

UART

FPGA

JTAG

FPGA I/O PinE2PROM


Floor Plan of Prototype PCB

Tektronix

Trigger Gain

On GainOff

On GainOff

A

B


Prototype Signal MeasurementPrototype Signal Measurement

FPGAFPGAAnalog Signal input

FPGA Output

Digital Output

FPGA Input

Digtal Signal input Analog Output

SpecFirstSpecFirst

SpecFirstSpecFirst

COMS影像元件架構


Analog LIN Out

20 X 20

CMOS APS

Imaging Area

20 X 20

CMOS APS

Imaging Area

Column Dual CDS CircuitsColumn Dual CDS Circuits

Horizontal Shift RegisterHorizontal Shift RegisterVideoAmp

VideoAmp

Analog XDR Out

Gain OffsetVe r

tical

Shi

f t R

egis

ter

Ve r

tical

Shi

f t R

egis

ter

Hclk

Hreset

Hdata

Bi-directional Bus Control

Bi-directional Bus Control

Dual 12-bit A/DConverter

Dual 12-bit A/DConverter

VADD[9.0] CDS andRESET


CMOS影像感測器之佈局


Image Sensor Chip


Mechanism of Image Sensor


Timing Diagram of Image Sensor

Image output for video mode(by parallel)

Addr[7..0]

XYSel

ADClk

Data[7..0]

Ready

nDstrb

nWait

R_OutputImgData:mov A,@0x78mov Count,A

mov A,YBeginmov YCount,A

LOutLine:inc Ycountmov A,Ycountmov PORT6,Anopbs PORT8,XYSELbc PORT8,XYSELcall Delay10us

mov A,@0xa0mov Count1,A

LOutPixel:

mov A,Count1add A,XSub

LCheckWantRead:jbc PORT9,nDstrbjmp LCheckWantRead

mov PORT6,A

nopnopnopbc PORT8,ADCLKbs PORT8,ADCLK

bs PORT9,nWait

LCheckReadDone:jbs PORT9,nDstrbjmp LCheckReadDone

bc PORT9,nWait

djz Count1jmp LOutPixel

djz Countjmp LOutLineret

10us

10us

Line i An An-1 An-2 An-3

Dn Dn-1 Dn-2 Dn-3

10us

10us

Line i+1 An An-1 An-2

Dn Dn-1 Dn-2 Dn-3

An-3

We can implement the timing by hardware but we must add 3 bit for control.

(1) Control bit : 1 ==> start transmit, 0 ==> disable

(2) Indicatation bit : 1 ==> transmit finish, 0 ==> transmitting

(3) Transmit error bit : 1 ==> transmit error, 0 ==> transmit OK!

For flexible using, we can design a control bit to set the timing be operated by hardware or firmware

(1) operate mode : 1 ==> by hardware, 0 ==> by firmware!

50ns

Decided by PCtransmission time

ta+tbta : 50ns (typical)tb : 20~30ns


A/D Converter I/O Pin

3-Bit VoltageEstimator

3-Bit FlashA/D

Converter

DAC M

+-

3

3

Decoder

OuputLatch and

Tri-stateBuffers

TIMING AND CONTROL CIRCUITRY

OFL* DB7(MSB)

DB6

DB5

DB4

DB3

DB2

DB1 DB0(LSB)

MODE CS RD WR/RDY

A0**

INT

VREF+ VREF-

VIN*,VIN1**

V+

GND

*ADC08061**ADC08062

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20Vin

DB0

DB1

DB2

DB3

WR/RDY

MODE

RD

INT

GND

V+

NC

OFL

DB7

DB6

DB5

DB4

CS

VREF+

VREF-

圖(24) ADC08061的IC接腳圖


A/D Controller and Sensor Controller Signal


PS/2 Quadrature Input

7)BY,(1 ,7)BX,(1 ≤=∆≤≤=∆≤ AYfYAXfX

+1 +1 +1 +1 +1 -1 -1 -1 -1 -1


PS/2 Quadrature Output Waveform

ONE

XA/YA

XA/YA

XA/YA

XA/YA

XA/YA

XB/YB

XB/YB

XB/YB

XB/YB

XB/YB

TWO

THREE

FOUR

FIVE

圖(31) 正交信號表示法


PS/2 Output Data


Prototype System Measurement


Mouse Pad Material

膠質(8bit-1200dpi) 尼龍布(8bit-1200dpi)

A4紙(8bit-1200dpi) 蠟質(8bit-1200dpi)


Mouse Pad Material

相片(8bit-1200dpi) 皮革(8bit-1200dpi)

桌面(8bit-1200dpi) 白紙(8bit-1200dpi)


Image Sample Data

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 86 85 85 83 83 82 82 82 82 82 82 81 81 81 81 81 81 82 186 85 85 84 84 84 84 84 83 83 82 81 81 81 81 81 82 82 285 85 84 84 84 83 83 83 82 82 82 81 81 81 80 80 84 84 386 84 84 83 83 82 82 82 81 81 81 81 81 81 81 81 81 81 486 84 84 83 83 81 80 81 81 81 82 81 82 81 81 82 82 82 587 85 84 84 84 82 81 82 81 82 83 82 82 83 82 82 83 83 686 84 84 83 83 82 81 82 81 82 82 82 82 82 82 82 82 82 787 85 85 84 83 83 82 83 82 83 83 83 83 83 83 83 83 82 888 86 86 85 84 83 83 83 83 84 84 84 84 83 83 83 83 82 988 87 87 86 86 84 83 84 83 84 84 84 84 83 83 83 83 83 1089 87 87 85 86 84 83 84 84 84 84 84 84 84 83 84 84 84 1188 86 85 85 85 84 83 83 83 84 84 83 84 84 84 84 84 85 1287 86 85 84 85 84 83 84 83 84 84 83 83 84 84 84 84 83 1387 86 85 84 85 84 83 84 83 83 83 83 83 83 83 83 83 83 1488 87 87 87 87 84 83 83 83 83 84 84 84 84 84 83 84 84 1587 87 87 87 86 84 82 83 83 83 84 84 84 85 84 84 84 85 1687 86 86 86 85 83 82 83 83 84 84 84 84 84 84 84 84 86 1787 86 85 85 85 83 82 83 82 83 84 83 83 84 83 84 84 84 18

The Output of ADC Chip:

18*18 Pixel/Frame


Image Data Analysis1 3 5 7 9

11 13 15 17 S1

S6

S11

S16

0

10

20

30

40

50

60

70

80

90

100

90-100

80-90

70-80

60-70

50-60

40-50

30-40

20-30

10-20

0-10Image Frame 1

Gray level value

one Sensor line

Frame number


Consecutive Image Data Analysis

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18S1

S6

S11

S16

0

20

40

60

80

100

120

140

160

180

160-180

140-160

120-140

100-120

80-100

60-80

40-60

20-40

0-20

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18S1

S6

S11

S16

0

20

40

60

80

100

120

100-120

80-100

60-80

40-60

20-40

0-20

Image Frame 2 Image Frame 3


Mouse Track Analysis

Real Track

Prototype Track


Mouse Track Analysis

Error Source:

1. Sensor Noise

2. A/D QuantizationReal Track

Prototype Track


Refined Modification and Re-Test



Error Vertical Track Final Modified Result



Error Horizontal Track Final Modified Result



Prototype Track

Real Track

Complete Match

Error Elliptical Track Final Modified Result


成果驗證成果驗證

以下是利用PC-based Logic Analysisor所顯示的結果


Chip Floor PlanChip Floor Plan

ImageSensor

IP

ADCIP

Digital Circuits

IP

CLCC


FPGA DeviceFPGA DeviceFPGA Device

FPGA Design Flow & SynthesisFPGA Design Flow & SynthesisFPGA Design Flow & Synthesis

DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform

DIP Prototype System MeasurementDIP Prototype System MeasurementDIP Prototype System Measurement

Design Example


Design Example -Square Root Algorithm

Feature:Shift operations instead of multiplications.Without the need to resort to multiplications or divisions.Advantageous in terms of both area & timing.Parameterizable.


Algorithm Presentation

Uses unsigned integers to represent.Based on bisection method.The algorithm presented by E . W. Dijkstra .Find a non negative integer a satisfying the following constraints:

2arg root remainder= +


Advance Version –Add Fraction Part (1)

Algorithm 1: (approximation) Use Remainder part to convert it.I find one regular rule as the following:

The differential value are regular between

radicands

We see the differential value are regular , so we can use divider or shifter operator to convert the remainder to fraction part.Ex. I chose radicand is 6 , so I get the root equal 2 and remainder equal 2 . I know the differential value of radicand is 5 between root equal 2 and 3 , so the fraction part = 2/5=0.4 (approximation).


Advance Version –Add Fraction Part (2)

Algorithm 2: (Accurate) Use Radicand part to convert it.Only require shift operator and can obtain higher accuracy.General formula :

EX. We choose radicand is

( ){ } ( ){ }:

, :2

: 2 2

n Radicand bitsinterger n minterger n m dot point M for m Extend Radicand bits

mM mM

⎧⎡ ⎤ ⎨⎣ ⎦ ⎪

⎪ =⎩

( ) ( )( 12)7 (0000 _ 0111) 0000 _ 0111_ 0000 _ 0000 _ 0000

600 _1010 _1001.

0010.101001 2.641

left shift m bitsradicand

square root dot point right shift M bits

So We can get a solution is

⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→

⎯⎯⎯⎯⎯⎯⎯⎯→ ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→

− =

=

≈


Design Flow

nLint : Novas nLintCode Coverage : TransEDA VN

Simulation : Modelsim or Quartus II Waveform (.wlf)Testbench :

Xilinx HDL Bencher Synapti CAD TestBencher Pro Diagonal BestBench

Compilation : Quartus II

Synthesis : Synplicity Synplify


Hardware Design- APB InterfaceAMBA APB Transfer Protocol:

Require two clock cycle to completethe write or read operation.


Hardware Design- APB Interface

AMBA APB W/R Transfer


APB Wrapper & Interface Architecture


User Programming Model

RDYRFDxxxxxxxxxxxxxxxxxx

Status Register.28bits 1bit 1 bit 1 bit 1bit

Memory Mapped DFF Status Register

DFFsDFF_W DFF_R

Address mapping range

Address space

0x0000_0000

0x0000_0050D Q D Q

Interrupt

Int_gen

If the square root calculate complete,The interrupt occur & RDY set “1”

0 0


Hardware Circuit (Top Level)

srt_module

U_U3

s_clk_clocks_rst_n_as_load

[7:0] s_radicand[7:0]

s_done_r[7:0]s_srt[7:0]

interface_module

U_U2

s_clk_clocks_clk_ens_rst_n_as_sels_w_rs_done

[2:0] s_addr_dec[2:0][31:0] s_apb_data_in[31:0][7:0] s_srt_nxt[7:0]

s_int_gens_load

[7:0]s_radicand_r[7:0][31:0]s_apb_data_out[31:0]

wrapper_module

U_U1

s_selx[31:0] s_addr[31:0]

[2:0]s_addr_dec[2:0]

s_prdata[31:0][31:0]

s_interrupts_pwdata[31:0] [31:0]

s_paddr[31:0] [31:0]

s_pwrite

s_pselx

s_prst_n

s_penable

s_clk_pclk


Hardware Circuit (Wrapper)

if (s_selx==1'b1 && s_addr[ÀDDR_UP-1 : ÀDDR_UP-4]==`FIFO_W_ADDR )s_addr_dec = `NUM_DECODER'b001;

else if (s_selx==1'b1 && s_addr[ÀDDR_UP-1 : ÀDDR_UP-4==`FIFO_R_ADDR)s_addr_dec = `NUM_DECODER'b010;

else if (s_selx==1'b1 && s_addr[ÀDDR_UP-1 : ÀDDR_UP-4]==`FIFO_ST_REG)s_addr_dec = `NUM_DECODER'b100;

elses_addr_dec = `NUM_DECODER'b000;

Address decode to DFF_W

Address decode to DFF_R

Address decode to Status Registers

addr_dec_proc_s_addr_dec20



addr_dec_proc_un1_s_addr_1<

[7:4]

1100

addr_dec_proc_un1_s_addr<

[7:4]

0110

s_w_addr_dce[2:0]

s_paddr[31:0] [31:0]

s_pselx


Hardware Circuit (Interface)

s_apb_data_out_1[7:0]

0

1

[2]

[7:0][7:0]

s_st_reg_rfd

ed

ed

ed

ed

ed

ed

0

1

[1]0

[3]0

1

0

s_load

ed

ed

ed

0

[3]1

[2]

s_int_gen

ed

ed

ed

0

1

[2]

un1_s_cur_state_6

[2]

un1_s_cur_state_5

[2]

un1_s_cur_state_4

[0]

un1_s_cur_state_3

[0]

un1_s_cur_state_2[1]

ed

ed

ed

ed

[0]0

[1]0

[2]1

[3]1

statemachine

s_cur_state[3:0]

I[2:0][3:0]Q[3:0]C

R

un1_s_st_reg_rdy32

un1_s_cur_state_1

[2]

seq_fsm_proc_s_st_reg_rdy32

[1]

s_srt_q_r[7:0]

R

[7:0]Q[7:0][7:0] D[7:0]E

seq_fsm_proc_s_st_reg_rfd10

[0]

s_radicand_r[7:0]

R

[7:0]Q[7:0][7:0] D[7:0]E

read_reg_proc_s_srt_q_r6

[1]

un1_s_cur_state

[3]

write_reg_proc_s_radicand_r6

[0]

s_prdata[31:0]

s_w_load

s_interrupt

s_w_radicand[7:0][7:0]

s_w_srt[7:0] [7:0]

s_pwdata[31:0] [31:0]

s_w_addr_dce[2:0] [2:0]

s_w_done

s_pwrites_pselx

s_prst_n

s_penable

s_clk_pclk

000000000000000000000000[7:0]

00000

0

The FSM is used generated flags Interrupt generation


Simulation

APB Protocol Signals

Address Bus

Square Roots

Radicand data


n-Lint

These warnings include:1. Bit width mismatch in assignment.2. FSM and non-FSM logic in same

module.So the total warnings are 4 in my design.


Code CoverageUse TransEDA VN v.2002.05 to Run code coverage

Code Coverage. We see the all coveragesreach 100% , but VN can’t detect my FSMin interface_module.


FloorPlan View

Carry Chain :-------------------------Length number

15 116 217 1


Resource

Target Dveice EPF10K30EFC256-1FlipFlops 58Logic elements 157/1728 (9 %)Pins 102/102 (57 %)EAB bits 0/24576 (0 %)Fan-out 467fmax 107.53Mhz

(period=9.3ns)


Download to Integrator

My Results


FPGA Environment Platform

Nios Development board

PC-based Logic Analyzer

Signals Probe


FPGA Verification Result

The verification result for PC-based logic analyzer


FPGA Summary


FPGA Hierarchy


Floorplan View


FPGA Post-Synthesis Resource


FPGA fmax


Logic Synthesis – Synopsys (1)

Wrapper_moduleSrt_module

Interface_module



Wrapper_module



Interface_module



Srt_moduleDw01_add

Dw01_sub

Dw01_cmp2

Dw01_add



Critical path

OK !


REFERENCES

http://www.cic.edu.tw/chip_design國科會CIC中心

Altera hhtp://www.altera.comhhtp://www.altera.com/IPmegastore

XILINX http://www.xilinx.com/products

廠商: http://www.zeepe.com.tw廠商: http://www.chirkal.com.tw

儀器: http://www.tek.com儀器: http://www.hp.com

http://www.cic.edu.tw/chip_designhttp://www.xilinx.com/productshttp://www.zeepe.com.tw/http://www.chirkal.com.tw/http://www.tek.com/http://www.hp.com/


REFERENCE BOOKS

[1] K. Coffman, Real Workd FPGA Design with Verilog, Prentice Hall PTR, 1999.[2] M. B. Uwe, Digital Signal Processing with Field Programmable Gate Arrays,

Springer Verlag, 2001.[3] C. Scholl, Functional Decomposition with Applications to FPGA Synthesis,

Kluwer Academic Publishers, 2001.[4] J. O, Hamblen, M. D. Furman, Rapid Prototyping of Digital Systems,

Kluwer Academic Publishers, 2001.[5] J. V. Oldfield and R. C. Dorf, Field-Programmable Gate Arrays: Reconfigurable

Logic for Rapid Prototyping and Implementation of Digital Systems,[6] J. Bergeron, Writing Testbenches - Functional Verification of HDL Models

, Kluwer Academic Publishers, 2000.[7] D. J. Smith, Hdl Chip Design: A Practical Guide for Designing, Synthesizing &

Simulating Asics & Fpgas Using Vhdl or Verilog, Doone Pubns, 1998.[8] Soild-State Optical Mouse Sensor with PS/2 and Quadration Outputs，

HP databook, 2000.


REFERENCES

國外光學滑鼠製造商http://www.atek.com/accessories/minimouse.htm.http://www.store.yahoo.com/ibselec/index.html.http://shop.store.yahoo.com/colorcase-store/crysopmous.html.http://www.usbman.com/Reviews/belkin_optical_mouse.htm.http://www.aopen.com/products/mice/o35g.htm.

國內光學滑鼠製造商http://www.gowisdom.com.tw.http://www.gigabyte.com.tw/chinese-web/news.http://www.tcstar.com.tw/product_mouse_opt.htm.http://www.btc.com.tw/btc2001_c/news_9.html.http://hk.tom.com/poptech/product/hard/periph.

光學滑鼠控制晶片設計商http://www.microsoft.com/Taiwan/products/hardwarehttp://www.semiconductor.agilent.com/cgi-bin/morpheus

http://www.atek.com/accessories/minimouse.htmhttp://www.store.yahoo.com/ibselec/index.htmlhttp://shop.store.yahoo.com/colorcase-store/crysopmous.htmlhttp://www.usbman.com/Reviews/belkin_optical_mouse.htmhttp://www.aopen.com/products/mice/o35g.htmhttp://www.gowisdom.com.tw/http://www.tcstar.com.tw/product_mouse_opt.htmhttp://www.btc.com.tw/btc2001_c/news_9.htmlhttp://hk.tom.com/poptech/product/hard/periph

COMS影像元件架構CMOS影像感測器之佈局Algorithm PresentationAdvance Version – Add Fraction Part (1)User Programming Model

FPGA Design Flow & SynthesisFPGA Design Flow & Synthesis•™材.pdf · 2015-09-17 ·...

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Transcript of FPGA Design Flow & SynthesisFPGA Design Flow & Synthesis•™材.pdf · 2015-09-17 ·...