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Paulo N.M. Sampaio

Arquitectura de Sistemas Computacionais

Prof. Dr. Paulo Sampaio

Universidade da Madeira - UMA

Paulo N.M. Sampaio

Organização da disciplina

Programa Teórico

1. Introdução (IPCHW 1)

2. Microprocessadores para PCs (IPCHW 3-14)

3. Chips de Memória (IPCHW 15)

4. Chipsets (IPCHW 16)

5. Interrupções e DMA (IPCHW 17)

6. RAM CMOS e RealtimeClock (IPCHW 18, 19)

7. Arquitecturas e Sistemas de BUS (IPCHW 20, 22, 25)

8. Dispositivos de Amazenamento (IPCHW 28, 29, 30, 31)

9. Periféricos (IPCHW 32, 33, 34, 35, 37)

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Input/Output Problems

• Wide variety of peripherals– Delivering different amounts of data

– At different speeds

– In different formats

• All slower than CPU and RAM

• Need I/O modules w/ some “intelligence”

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Input/Output Module

• Interface to CPU and Memory

• Interface to one or more peripherals

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Generic Model of I/O Module

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External Devices

• Human readable (human interface)– Monitor, printer, keyboard, mouse

• Machine readable– Disk, tape, sensors

• Communication– Modem

– Network Interface Card (NIC)

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External Device Block Diagram

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Read/Write, Report status,

etc.

Read/Not Ready (…)

Devices´soperations

Converts Data(e.g., electrical->,

->electrical

Holds dataI/O module-environment

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I/O Module Function• Control & Timing

– Coordinate the flow of traffic between internal resources and external devices

• CPU (Processor) Communication– The I/O module must communicate with the processor and with the external

device (command decoding, data, status reporting and address recognition)

• Device Communication– Which involves commands, status information and data

• Data Buffering– In order to handle different transfer rates between main memory/processor and

peripheral devices

• Error Detection (e.g., extra parity bit)

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I/O Steps

1. CPU checks (interrogates) I/O module device status

2. I/O module returns status

3. If ready, CPU requests data transfer by sending a command to the I/O module

4. I/O module gets a unit of data (byte, word, etc.) from device

5. I/O module transfers data to CPU

Variations of these steps for output, DMA, etc.

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Need for Data Buffering: Typical I/O Data Rates

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I/O Module Diagram

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I/O Module Decisions

• Hide or reveal device properties to CPU

• Support multiple or single device

• Control device functions or leave for CPU

• Also O/S decisions– e.g. Unix treats everything it can as a file

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Input Output Techniques

• Programmed I/O

• Interrupt driven

• Direct Memory Access (DMA)

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Programmed I/O

• CPU has direct control over I/O– Sensing status

– Read/write commands

– Transferring data

• CPU waits for I/O module to complete operation

• Wastes CPU time

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Programmed I/O - detail

1. CPU requests I/O operation

2. I/O module performs operation

3. I/O module sets status bits

4. CPU checks status bits periodically

5. I/O module does not inform CPU directly

6. I/O module does not interrupt CPU

7. CPU may wait or come back later

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I/O Commands

• CPU issues address– Identifies module (and device if >1 device per module)

• CPU issues command– Control - telling module what to do

• e.g. spin up disk

– Test - check status• e.g. power? Error?

– Read/Write• Module transfers data via buffer from/to device

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Addressing I/O Devices

• Under programmed I/O data transfer is very like memory access (CPU viewpoint)– I/O instructions that the processor fetches from memory, and the I/O commands

that the processor issues to an I/O module to execute the instructions => one to one relationship

• The form of the instruction depends how the external devices areaddressed:

– Each device given unique identifier

– CPU commands contain identifier (address)

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Interrupt Driven I/O

• Overcomes CPU waiting

• No repeated CPU checking of device

• I/O module interrupts when ready

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Interrupt Driven I/OBasic Operation

1. CPU issues read command

2. I/O module gets data from peripheral whilst CPU does other work

3. I/O module interrupts CPU

4. CPU requests data

5. I/O module transfers data

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CPU Viewpoint

1. Issue read command

2. Do other work

3. Check for interrupt at end of each instruction cycle

4. If interrupted:-– Save context (registers)– Process interrupt

• Fetch data & store

See Operating Systems notes …

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Design Issues

• How do you identify the module issuing the interrupt?

• How do you deal with multiple interrupts?– i.e. an interrupt handler being interrupted

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Identifying Interrupting Module (1)

• Different line for each module– PC– Limits number of devices

• Software poll– CPU asks each module in turn

– Slow

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Identifying Interrupting Module (2)

• Daisy Chain or Hardware poll– Interrupt Acknowledge sent down a chain

– Module responsible places vector on bus

– CPU uses vector to identify handler routine

• Bus Master– Module must claim the bus before it can raise interrupt

– Only one module can raise the line at a time

– e.g. PCI & SCSI

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Multiple Interrupts

• Each interrupt line has a priority

• Higher priority lines can interrupt lower priority lines

• If bus mastering, only current master can interrupt

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Example - PC Bus

• 80x86 has one interrupt line

• 80x86 based systems use one 8259A interrupt controller

• 8259A has 8 interrupt lines (modules)

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Sequence of Events

1. 8259A accepts interrupts

2. 8259A determines priority

3. 8259A signals 8086 (raises INTRequest line)

4. CPU Acknowledges (INTA line)

5. 8259A puts correct vector on data bus

6. CPU processes interrupt

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82C59A InterruptController

A 82C59A is programmable => The 80x86

Determines the priority scheme to be used

By setting a control word in the 82C59A.

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Intel 82C55A Programmable Peripheral Interface

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The 82C55A is used for Programmed I/O and Interrupt-Driven I/O

External interfaceInternal interface

control

data

status

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Using 82C55A To Control Keyboard/Display

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DMA Function

• Additional Module (hardware) on bus

• DMA controller takes over from CPU for I/O

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DMA Module Diagram

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DMA Operation

1. CPU tells DMA controller:-– Read/Write– Device address– Starting address of memory block for data– Amount of data to be transferred

2. CPU carries on with other work

3. DMA controller deals with transfer

4. DMA controller sends interrupt when finished

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DMA Transfer - Cycle Stealing

• DMA controller takes over bus for a cycle

• Transfer of one word of data

• Not an interrupt– CPU does not switch context

• CPU suspended just before it accesses bus– i.e. before an operand or data fetch or a data write

• Slows down CPU but not as much as CPU doing transfer

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DMA Configurations (1)

• Single Bus, Detached DMA controller• Each transfer uses bus twice

– I/O to DMA then DMA to memory

• CPU is suspended twice

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DMA Configurations (2)

• Single Bus, Integrated DMA controller

• Controller may support >1 device

• Each transfer uses bus once– DMA to memory

• CPU is suspended once

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DMA Configurations (3)

• Separate I/O Bus

• Bus supports all DMA enabled devices

• Each transfer uses bus once– DMA to memory

• CPU is suspended once

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I/O Channels

• I/O devices getting more sophisticated (Embedded processor and memory)

• e.g. 3D graphics cards

• CPU instructs I/O controller to do transfer

• I/O controller does entire transfer

• Improves speed– Takes load off CPU– Dedicated processor is faster

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I/O Channel Architecture

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Interfacing

• Connecting devices together

• Bit of wire?

• Dedicated processor/memory/buses?

• E.g. FireWire, InfiniBand

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IEEE 1394 FireWire

• High performance serial bus

• Fast

• Low cost

• Easy to implement

• Also being used in digital cameras, VCRs and TV

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Simple FireWire Configuration

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FireWire Configuration

• Daisy chain

• Up to 63 devices on single port– Really 64 of which one is the interface itself

• Up to 1022 buses can be connected with bridges

• Automatic configuration

• No bus terminators

• May be tree structure

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FireWire 3 Layer Stack

• Physical– Transmission medium, electrical and signaling characteristics

• Link– Transmission of data in packets

• Transaction– Request-response protocol

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FireWire Protocol Stack

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FireWire - Physical Layer

• Data rates from 25 to 400Mbps

• Two forms of arbitration (only one device at a time will transmit data)– Based on tree structure

– Root acts as arbiter

– First come first served

– Natural priority controls simultaneous requests• i.e. who is nearest to root

– Fair arbitration

– Urgent arbitration

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FireWire - Link Layer

• Two transmission types

– Asynchronous• Variable amount of data and several bytes of transaction data

transferred as a packet• To explicit address• Acknowledgement returned

– Isochronous• Variable amount of data in sequence of fixed size packets at regular

intervals• Simplified addressing• No acknowledgement

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FireWire Subactions

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InfiniBand

• I/O specification aimed at high end servers– Merger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation

I/O (Intel)

• Version 1 released early 2001

• Architecture and spec. for data flow between processor and intelligent I/O devices

• Intended to replace PCI in servers

• Increased capacity, expandability, flexibility

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InfiniBand Architecture

• Remote storage, networking and connection between servers

• Attach servers, remote storage, network devices to central fabric of switches and links

• Greater server density

• Scalable data centre

• Independent nodes added as required

• I/O distance from server up to – 17m using copper– 300m multimode fibre optic– 10km single mode fibre

• Up to 30Gbps

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InfiniBand Switch Fabric

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InfiniBand Protocol Stack

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Organização da disciplina

Programa Teórico

1. Introdução (IPCHW 1)

2. Microprocessadores para PCs (IPCHW 3-14)

3. Chips de Memoria (IPCHW 15)

4. Chipsets (IPCHW 16)

5. Interrupções e DMA (IPCHW 17)

6. RAM CMOS e RealtimeClock (IPCHW 18, 19)

7. Arquitecturas e Sistemas de BUS (IPCHW 20, 22, 25)

8. Dispositivos de Amazenamento (IPCHW 28, 29, 30, 31)

9. Periféricos (IPCHW 32, 33, 34, 35, 37)

Paulo N.M. Sampaio

Prof. Dr. Paulo Sampaio

Universidade da Madeira - UMA

Arquitectura de Sistemas Computacionais