CONTROLO DE UM DIRIGÍVEL - ltodi.est.ips.ptltodi.est.ips.pt/aabreu/relatoriofinal_dirigivel.pdf ·...

PROJECTO I EM ENGª ELECTRÓNICA E COMPUTADORES

CONTROLO DE UM DIRIGÍVEL

JOÃO ALEXANDRE Nº 3408 SÉRGIO ALMEIDA Nº 3594

24 DE OUTUBRO DE 2003

Escola Superior de Tecnologia de Setúbal Projecto Final de Curso

ESCOLA SUPERIOR DE TECNOLOGIA DE SETÚBAL

INSTITUTO POLITÉCNICO DE SETÚBAL

DEPARTAMENTO DE ENGENHARIA

ELECTROTÉCNICA

CONTROLO DE UM

DIRIGÍVEL

João Alexandre Sérgio Almeida

Projecto para obtenção do Bacharelato em Engª Electrónica e Computadores

Outubro de 2003

Instituto Politécnico de Setúbal I


Projecto realizado sob a orientação do

Prof. António Abreu

Departamento de Engenharia Electrotécnica

Escola Superior de Tecnologia de Setúbal

Instituto Politécnico de Setúbal

Instituto Politécnico de Setúbal II


Agradecimentos Em primeiro lugar há que salientar a elevada importância do Prof. António Abreu que apresentou uma “infinita” disponibilidade durante todo o decorrer do projecto, disponibilidade esta que permitiu o esclarecimento de dúvidas que foram surgindo ao longo do tempo. O contributo dos seguintes colegas foi também muito importante para a realização deste projecto. Agradecimentos aos colegas Marco Silva e Rui Pimenta, pelo apoio dado no que diz respeito a fornecimento de material necessário e também pelos conhecimentos úteis. A todos os colegas que realizaram os seus projectos, que contribuíram dando apoio e incentivo. Há que referir a disponibilidade mostrada por um dos funcionários da empresa Balão Balão, no que diz respeito ao fornecimento de Hélio e ao contributo para o aumento de conhecimentos úteis ao projecto. Por último, há que referir o contributo do Sr. Vítor Neves pelos conhecimentos relativamente a uma ferramenta de software que foi utilizada.

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Resumo Este trabalho tem como objectivo o desenvolvimento de um controlador de um dirigível a hélio, de modo a que este se possa deslocar num ambiente tridimensional. O dirigível é composto por um balão, três motores de corrente contínua e sensores ópticos. Dois dos motores controlam o deslocamento do Balão na horizontal, tendo o outro motor a função de controlar o Balão na vertical. Os sensores determinam a distância do balão aos obstáculos que estejam na direcção do eixo dos sensores. São apresentados os pormenores relativos aos desenvolvimentos realizados (software e hardware) e são mostrados dois exemplos de controlo sobre o balão. O primeiro exemplo assenta num controlo da altitude e o segundo num sistema autónomo simples, denominado Robot Minimalista.

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Abstract The purpose of this work is to develop an autonomous system that has ability to fly on a three-dimensional environment. A blimp, three DC motors and optical sensors compose the system. Two motors control the horizontal movements of the system. The third motor controls the system movement in the vertical. The sensors determine the distance between the Blimp and obstacles that are in the sensor axis direction. All details regarding the development of the project (software and hardware) are shown, as are two examples of control over the blimp. The first example shows an altitude control of the blimp and the second is based on a very simple autonomous system, called Robot Minimalista.

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Palavras Chave Sensor Controlo Dirigível Motor Hélio Estabilidade

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Keywords Sensor Control Blimp Motor Helium Stability

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Índice 1. Introdução ................................................................................................................... 1

1.1 Abordagem Genérica .......................................................................................... 1 1.2 Organização do Relatório do Projecto ................................................................ 2

2. Dirigível ...................................................................................................................... 3 2.1 Aquisição do Dirigível........................................................................................ 3 2.2 Características do Dirigível................................................................................. 3

2.2.1 Motores ....................................................................................................... 4 2.2.1.1 Motores de corrente contínua.................................................................. 4 2.2.1.2 Motores do Balão.................................................................................... 5

2.2.2 Cockpit........................................................................................................ 6 2.2.3 Balão ........................................................................................................... 7

2.2.3.1 Tipos de Balões....................................................................................... 7 2.2.3.2 Calculo do peso suportado pelo Balão utilizado..................................... 7 2.2.3.3 Estabilidade do Balão ........................................................................... 10

2.2.3.3.1 Testes efectuados ............................................................................ 11 2.2.3.3.2 Resultados ....................................................................................... 11

3. Hardware Desenvolvido............................................................................................ 14 3.1. Controlo de Motores ......................................................................................... 14

3.1.1 PWM......................................................................................................... 14 3.1.2 Controlo do sentido de rotação ................................................................. 15 3.1.3 Ponte em H................................................................................................ 16 3.1.4 CPLD ........................................................................................................ 17

3.2 SENSORES....................................................................................................... 17 3.2.1 SENSOR DE MEDIÇÃO DE DISTÂNCIAS .......................................... 17

3.2.1.1. Caracterização do Sensor.................................................................. 18 3.3. ADCs................................................................................................................. 19 3.4. FOTOTRANSÍSTORES................................................................................... 22 3.5. LDRs ................................................................................................................. 24 3.6. ALIMENTAÇÃO ............................................................................................. 26

4. Experiências.............................................................................................................. 27 4.1. Controlo de Altitude ......................................................................................... 27

4.1.1 Controlo em malha fechada ...................................................................... 27 4.1.1.1. Acção proporcional........................................................................... 28 4.1.1.2. Acção Integral................................................................................... 29 4.1.1.3. Acção Derivativa .............................................................................. 30

4.1.2 Software de Controlo ................................................................................ 31 4.1.3 Resultados ................................................................................................. 32

4.2 Robot Minimalista ............................................................................................ 39 5.1 Conclusões ........................................................................................................ 43 5.2 Futuros desenvolvimentos ................................................................................ 44

Referências Bibliográficas ................................................................................................ 45

Instituto Politécnico de Setúbal VIII


Lista de Figuras Figura 2. 1 - Cockpit do Dirigível....................................................................................... 3 Figura 2. 2- Caracterização da rotação de um motor corrente contínua ............................. 5 Figura 2. 3 – Hélice de um dos motores do Dirigível......................................................... 6 Figura 2. 4 – Desenho do Balão em AutoCad .................................................................... 8 Figura 2. 5 - Calculo do volume do Balão .......................................................................... 8 Figura 2. 6 - Forças que actuam sobre o Dirigível............................................................ 10 Figura 2. 7 - Balão com fios.............................................................................................. 11 Figura 2. 8 – Gráfico da altitude do balão com fios lançado abaixo do PE...................... 12 Figura 2. 9 – Gráfico da altitude do balão com fios lançado acima do PE....................... 12 Figura 3. 1 - Circuito PWM .............................................................................................. 15 Figura 3. 2 - Circuito descodificador ............................................................................... 15 Figura 3. 3 - Ponte H......................................................................................................... 16 Figura 3. 4 - Sensor de infravermelhos............................................................................. 18 Figura 3. 5 - Caracterização do sensor relativamente a objectos de diferentes cores....... 18 Figura 3. 6 – Tipo de ADCs quanto ao Interface.............................................................. 19 Figura 3. 7 – Resposta Característica do ADC ................................................................. 20 Figura 3. 8 – Ciclo de conversão do ADC (MAX1112) ................................................... 21 Figura 3. 9 – Fototransistor............................................................................................... 22 Figura 3. 10 - Resposta do fototransistor face às diferentes cores.................................... 22 Figura 3. 11 - Circuito implementado para o Fototransistor............................................. 23 Figura 3. 12 - LDR............................................................................................................ 24 Figura 3. 13 - Ligação do LDR......................................................................................... 24 Figura 3. 14 - Circuito implementado para medir a tensão no LDR................................. 25 Figura 3. 15 - Bateria (Idêntica à utilizada) ...................................................................... 26 Figura 4. 1 - Controlo proporcional .................................................................................. 28 Figura 4. 2 - Controlo Integral .......................................................................................... 29 Figura 4. 3 - Controlo Derivativo ..................................................................................... 30 Figura 4. 4 – Janela do Software realizado ....................................................................... 31 Figura 4. 5 - Controlo proporcional com Kp = 5 .............................................................. 32 Figura 4. 6 - Controlo proporcional com Kp = 10 ............................................................ 32 Figura 4. 7 - Controlo proporcional com Kp = 15 ............................................................ 33 Figura 4. 8 - - Controlo proporcional com Kp = 20......................................................... 33 Figura 4. 9 - Controlo Pd com Kd = 5 .............................................................................. 34 Figura 4. 10 - Controlo Pd com Kd = 7 ............................................................................ 34 Figura 4. 11 - Controlo Pd com Kd = 9 ............................................................................ 35 Figura 4. 12 - Controlo Pi com Ki = 1 .............................................................................. 36 Figura 4. 13 - Controlo Pi com Ki = 2 .............................................................................. 36 Figura 4. 14 - Controlo Pi com Ki = 3 .............................................................................. 37 Figura 4. 15 – Gráfico de altitude do balão com fios........................................................ 38 Figura 4. 16 – Gráfico de altitude do balão com fios passado uma hora.......................... 38 Figura 4. 17 – Cockpit do Dirigível com os LDRs e o Fototransistor acoplados ............. 39 Figura 4. 18 – Sinal à saída do circuito do PWM para um nível de luminosidade inferior

ao valor de referencia................................................................................ 40

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Figura 4. 19 – Foco de luz a incidir sobre o LDR do lado direito do cokpit do balão...... 41 Figura 4. 20 – Foco de luz a incidir sobre o Fototransistor .............................................. 42

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Lista de Tabelas Tabela 4. 1 – Peso de todos os componentes utilizados no Robot Minimalista ............... 42

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Lista de Abreviaturas ADC Conversor Analógico Digital CPLD Circuito de Lógica Programável LDR Resistência Variável com a Luz (Light Dependent Resistor) PWM Modulação em Largura de Pulso (Pulse Width Modulation) P Controlador Proporcional PD Controlador Proporcional-Derivativo PI Controlador Proporcional-Integral DC Corrente contínua (Direct current)

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1. Introdução Este capítulo encontra-se divido em duas partes. A primeira é relativa à caracterização do projecto, que passa primeiro por uma abordagem genérica à área em que o projecto se engloba, e por último, na particularização do sistema em questão, mostrando as possíveis aplicações que um projecto com estas características poderá ter. Na segunda parte é feita uma descrição da organização do relatório, nomeadamente o conteúdo geral de cada um dos capítulos.

1.1 Abordagem Genérica A robótica é uma área de investigação que tem despertado desde há muito tempo o interesse de muitas empresas. Tem-se como exemplo a empresa japonesa Honda, que desde algumas décadas tem vindo a desenvolver vários protótipos de robots terrestres. Robots estes que têm como objectivo parecerem-se o mais possível com um ser humano, no que diz respeito à forma e locomoção. No entanto, quando se fala de robótica aérea, a situação já é diferente. A investigação nesta vertente da robótica não se encontra tão desenvolvida. Como robots aéreos podem-se ter aviões, helicópteros e balões. As diferenças entre estes residem na sua constituição, o que requer tipos de controlo diferente. No caso dos aviões existe a necessidade de se atingir uma determinada velocidade, de modo a que o efeito aerodinâmico de sustentação funcione e o avião permaneça no ar. Com efeito, quando isso não acontece, o avião perde sustentação, podendo despenhar-se. Por seu turno, no helicóptero existe a possibilidade de o poder estabilizar num dado ponto, i.e., ter-se velocidade de deslocamento nula. Isto é possível devido à disposição dos motores. Por ultimo têm-se os balões. A sustentação de um balão no ar é garantida pelo composto químico que é utilizado para encher o mesmo. O balão é considerado o robot aéreo mais estável por não necessitar da actuação de motores para se sustentar no ar.

Instituto Politécnico de Setúbal 1


De referir duas das principais aplicações que os robots aéreos podem ter. A primeira aplicação refere-se a uma possível utilização em funções de entretenimento. A outra aplicação diz respeito à utilização em sistemas de vigilância (incêndios e aplicações militares). Neste documento relata-se o projecto do controlo de um balão a hélio com aproximadamente 120 litros de capacidade, adquirido recentemente pelo Departamento de Engenharia Electrotécnica da Escola Superior de Tecnologia de Setúbal do Instituto Politécnico de Setúbal. É descrito o projecto do controlo dos motores, baseado em microcontrolador, e são descritos os sensores utilizados. São ainda relatadas duas experiências de controlo com objectivos diferentes. Numa faz-se o controlo da posição em altitude, recorrendo a controladores P, PI e PD. Na outra descreve-se um sistema simples em que os sensores são ligados directamente aos motores. Em ambas as situações são realizadas experiências e discutidos os resultados. O balão revelou-se um sistema difícil de controlar, dado ser muito leve, ou seja, é muito sensível a interferências externas e praticamente não ser influenciado pelo atrito, ou seja, pequenos movimentos demoram muito tempo a desaparecer.

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Organização do Relatório do Projecto Este projecto encontra-se organizado em cinco capítulos:

No capítulo 2 caracteriza-se o Dirigível utilizado.

No capítulo 3 descreve-se o hardware desenvolvido.

No capítulo 4 vão ser descritas as experiências e discutidos os resultados obtidos.

Por fim, no capítulo 5 apresentam-se as conclusões do trabalho desenvolvido e as perspectivas de trabalho futuro.



2. Dirigível

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Este capítulo irá assentar inicialmente numa introdução relativamente à obtenção do dirigível, sendo posteriormente descritos todos os elementos que o constituem.

Aquisição do Dirigível De modo a realizar o projecto, foi necessário primeiro que tudo obter um balão e motores. Como tal foram realizadas inúmeras pesquisas na Internet com vista a este fim. Em Portugal os resultados da pesquisa foram praticamente nulos. Como tal optou-se por adquirir um dirigível a uma empresa sediada no estrangeiro, mais propriamente no Canadá.

Características do Dirigível A opção da compra de um dirigível foi uma mais valia em relação a uma possível compra de um balão e dos motores à parte. A mais valia reside no facto de o dirigível já trazer uma estrutura que suporta os motores e um cockpit que permite colocar uma possível electrónica e alimentação. Na Figura 2.1 pode ver-se a estrutura que suporta os motores e o cockpit do dirigível.

Figura 2. 1 - Cockpit do Dirigível



O dirigível adquirido é constituído por um pacote que engloba um balão, um cockpit que suporta os três motores, uma placa PCB com a electrónica de controlo dos motores e um comando de radio frequência para comandar o dirigível. Deste pacote foi aproveitado apenas o balão, o cockpit e respectivos motores. A possível utilização do modulo de RF que o balão trazia foi posta de lado devido a este ser Unidireccional.

2.2.1 Motores

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Nesta secção irá ser realizada uma introdução relativamente aos motores de corrente contínua, para depois ser feita uma caracterização dos motores utilizados no Dirigível.

2.2.1.1 Motores de corrente contínua Todos os motores eléctricos valem-se dos princípios do electromagnetismo, mediante os quais condutores situados num campo magnético e atravessados por correntes eléctricas sofrem a acção de uma força mecânica, por exemplo, electroímans exercem forças de atracção ou repulsão sobre outros materiais magnéticos. Na verdade, um campo magnético pode exercer força sobre cargas eléctricas em movimento. Como uma corrente eléctrica é um fluxo de cargas eléctricas em movimento num condutor, conclui-se que todo condutor percorrido por uma corrente eléctrica, imerso num campo magnético, pode sofrer a acção de uma força. Num motor há dois electroímans em que um impulsiona o outro. O electroíman tem algumas vantagens sobre um íman permanente:

Podemos torná-lo mais forte. O seu magnetismo pode ser criado ou suprimido. Os seus pólos podem ser invertidos.



Figura 2. 2- Caracterização da rotação de um motor corrente contínua Um íman permanente tem os pólos norte e sul definidos. Um electroíman também os tem mas a característica de cada pólo (norte ou sul) depende do sentido da corrente eléctrica. Quando se altera o sentido da corrente, a posição dos pólos também se altera, do norte para o sul e de sul para norte. Um dos electroímans de um motor tem uma posição fixa; está ligado à armação externa do motor e é chamado rotor . O outro electroíman está colocado no eixo de rotação e tem o nome de estator. Quando se liga o motor, a corrente chega à bobina do campo, determinando os pólos norte e sul. Há, também, o fornecimento de corrente ao íman da armadura, o que determina a situação norte ou sul dos seus pólos. Os pólos opostos dos dois electroímans atraem-se, como acontece nos imanes permanentes. O íman da armadura, tendo movimento livre, gira, a fim de que o seu pólo norte se aproxime do pólo sul do íman do campo e o seu pólo sul do pólo norte do outro. Se nada mais acontecesse, o motor pararia completamente. Um pouco antes de se encontrarem os pólos opostos, no entanto, a corrente é invertida no electroíman da armadura, (com o uso de um comutador) invertendo, assim a posição de seus pólos; o norte passa a ser o que está próximo ao norte do campo e o sul passa a ser o que está próximo ao sul do campo (Figura 2.1). Eles então repelem-se e o motor continua em movimento. Esse é o princípio de funcionamento do motor de corrente contínua.

2.2.1.2 Motores do Balão Como foi referido anteriormente, o Dirigível é constituído por 3 motores (Figura 2.1). Os motores são de corrente contínua e apresentam um tamanho e peso reduzidos. Na extremidade do eixo de cada um dos motores encontra-se acoplada uma hélice (Figura 2.3) que tem como função fazer deslocar o ar e assim movimentar o balão.



Figura 2. 3 – Hélice de um dos motores do Dirigível

Têm-se as seguintes características dos motores:

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2.2.2 Cockpit

A velocidade dos motores é máxima para um valor próximo dos 3 Volts; Para a velocidade máxima tem-se que o valor da corrente consumida ronda os 200mA para cada um dos motores; Os motores rodam nos dois sentidos; para mudar o sentido de rotação basta mudar a polaridade da alimentação.

O cockpit do balão apresenta um formato aerodinâmico e tem como função suportar os motores. Outra possível função do cokpit pode ser o sustento de alguma electrónica e uma possível bateria. Os dois motores laterais encontram-se suportados por uma haste que se encontra ligada ao cockpit. O outro motor encontra-se na parte detrás do Cockpit. O cockpit é feito de plástico, permitindo assim que seja o mais leve possível. A haste por outro lado é feita de um metal que apresenta alguma rigidez.



2.2.3 Balão Nesta secção faz-se uma introdução relativamente a balões, sendo posteriormente calculado o peso suportado pelo balão utilizado e analisada a estabilidade do mesmo.

2.2.3.1 Tipos de Balões Como materiais mais conhecidos para a construção de balões tem-se o látex e o foil. O látex é um material mais resistente que o foil mas que apresenta uma maior permeabilidade ao hélio ou hidrogénio. Por um lado, a resistência do balão é uma mais valia, pois permite que o balão aguente uma maior pressão relativamente aos balões de foil. Todavia a permeabilidade é uma grande desvantagem. Como tal, o dirigível utilizado é constituído por um balão de foil. O balão utilizado apresenta uma forma aproximada de um elipsoide.

2.2.3.2 Calculo do peso suportado pelo Balão utilizado

Tendo em vista que o sistema controlador irá ser suportado pelo balão, calculou-se o peso máximo que este é capaz de sustentar. De salientar que só através da obtenção desse peso se poderá saber a quantidade de electrónica a utilizar. Para calcular o peso máximo suportado pelo balão começou-se por calcular o volume. Puseram-se várias hipóteses para o cálculo do volume. Uma das hipóteses seria emergir o balão dentro de um depósito com água e verificar a diferença de nível antes e após emergir o balão. Esta hipótese foi posta de lado devido à diferença de pressões (água e hélio) ser muito grande. A técnica utilizada para calcular o volume do balão assentou na utilização de uma ferramenta que permite desenhar sólidos tridimensionalmente, permitindo posteriormente calcular o volume dos mesmos. A ferramenta utilizada foi o programa AutoCad, versão 2004.



Figura 2. 4 – Desenho do Balão em AutoCad Antes de se começar a utilizar o programa AutoCad, tiraram-se as medidas necessárias para a realização do desenho do balão, de modo a ficar o mais idêntico possível ao modelo original. Seguidamente, desenhou-se o balão (Figura 2.4) e por último cálculou-se o volume, recorrendo a uma das muitas funcionalidades do programa (Figura 2.5).

Figura 2. 5 - Calculo do volume do Balão



Como se pode observar o volume do balão anda na ordem dos 119,7 dm ³. De notar que o cálculo do peso máximo que o balão suporta foi efectuado com base nas características do composto químico utilizado para encher o balão. O composto químico utilizado foi o elemento He (Hélio). O hélio é obtido unicamente a partir de algumas explorações de gás natural, pelo que o seu custo é elevado. As principais fontes encontram-se nos EUA, Rússia e Argélia. O hélio é um gás nobre, incolor, inodoro, inerte e com uma densidade inferior à do ar, o que lhe confere o poder de elevação. Por cada metro cúbico de hélio irá obter-se um poder de elevação de aproximadamente 1Kg em condições normais, sendo de levar em conta que a variação das condições atmosféricas implica alterações. Como variáveis atmosféricas que afectam as propriedades do balão tem-se a humidade relativa, a temperatura e a pressão. Condições que favoreçam um aumento do volume de Hélio no interior do Balão podem ocasionar uma sobrepressão que pode colocar em causa a integridade dos utilizadores. Também a situação contraria pode originar situações de risco. Alem do hélio também se pode utilizar Hidrogénio, mas dado que se trata de um gás inflamável, a sua utilização neste tipo de aplicações é normalmente não aconselhada, carecendo o seu uso de um parecer especializado. Como foi descrito, o hélio puro é muito raro, sendo o seu preço em Portugal muito elevado. O seu uso é muito restrito. Apenas as estações meteorológicas o adquirem para uso. Não havendo assim a possibilidade de comprar hélio puro, a opção tomada foi adquirir hélio a uma empresa que vende outros compostos gasosos, tais como azoto e o hidrogénio. Como tal alugou-se uma botija de hélio de modo a poder encher o balão sempre que necessário. Através de informações dadas por um empregado da empresa, a botija adquirida contém cerca de 70% de hélio, sendo os outros 30% compostos mais densos.



Através de uma regra de três simples, cálculou-se o peso real suportado pelo balão.

119.7 g ----------- 100% X ----------- 65% X = 78 g Finalmente chegou-se à conclusão que o balão suporta aproximadamente 78 gramas. Subtraindo 40 gramas (cockpit, motores e estrutura que suporta os mesmos) fica-se com 38 gramas, para suportar o hardware a implementar.

2.2.3.3 Estabilidade do Balão Por estabilidade do balão entende-se um determinado intervalo de tempo onde o balão se encontra parado. Essa estabilidade vai ser garantida pela anulação de duas forças com sentidos opostos (Figura 2.6). a força gravítica (P) e a impulsão (I). Essa força é garantida pela quantidade de hélio que se encontra dentro do balão.

Figura 2. 6 - Forças que actuam sobre o Dirigível



2.2.3.3.1 Testes efectuados Foram feitos alguns testes referentes à estabilidade do Dirigível em duas situações distintas; em ambas é necessário adicionar peso para que o balão fique parado. A primeira situação diz respeito ao balão, no seu estado original e na segunda situação são colocados fios eléctricos (que conduzirão sinais eléctricos) como se pode ver na Figura 2.7. Outro dos testes realizados pretende avaliar a influência causada pelos fios no balão.

Figura 2. 7 - Balão com fios

2.2.3.3.2 Resultados No primeiro teste sentiu-se uma grande dificuldade em estabilizar o balão, devido a que este é suficientemente sensível ao acrescento de algumas miligramas. Adicionalmente o balão tem fugas de hélio com o passar do tempo, através das zonas de junção (zonas de soldadura do foil). Essas fugas alteram substancialmente as características do balão, o que torna difícil o estabilizar do balão.



Para o segundo caso a situação é diferente, pois o arco formado pelos fios vai fazer com que haja um auto- ajuste entre o peso do balão e a sua impulsão, que vai fazer com que haja estabilidade num determinado ponto denominado ponto de estabilidade ou PE.

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Figura 2. 8 – Gráfico da altitude do balão com fios lançado abaixo do PE

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Figura 2. 9 – Gráfico da altitude do balão com fios lançado acima do PE



Como se pode analisar pelas figuras 2.8 e 2.9, o balão com fios vai andar em torno de PE. Outra conclusão é que o balão não vai exercer a mesma força quando estiver acima do ponto de estabilidade ou abaixo, devido à influência dos fios. Quando o balão está acima do ponto de estabilidade o gráfico apresenta um comportamento quase estável, ou seja, vai ter um tempo de estabelecimento rápido; já quando o balão estiver abaixo do ponto de estabilidade, o balão vai ter um comportamento muito mais instável e um menor tempo de estabelecimento. As conclusões que se podem tirar é que os fios no balão vão interferir bastante com o balão, seja devido ao seu peso ou devido à sua rigidez. O fio é assim um factor de complexidade no balão.



3.

3.1.

3.1.1 PWM

Hardware Desenvolvido

Controlo de Motores Entende- se como controlo dos motores o controlo da velocidade e sentido de rotação dos mesmos.

Para controlar a velocidade de rotação dos motores será necessário controlar a tensão que se aplica aos terminais dos mesmos. A velocidade de rotação será imposta através da utilização de PWMs (Modulação em largura de Pulso). Este tipo de modulação tem por base manter a amplitude do pulso variando a sua largura, mas mantendo a frequência permitindo assim que a velocidade de rotação dos motores varie segundo o pulso que é transmitido aos mesmos. Basicamente o que está a ser feito é ligar e desligar a alimentação do motor, permitindo assim que esta varie entre 0 e o seu máximo. Na experiência referente ao Controlo da Altitude os PWMs foram implementados através de um contador e um comparador de 4 bits (Figura 3.1). De notar que também se podia ter implementado os PWMs recorrendo ao microcontrolador, através dos contadores. Mas como são necessários 3 PWMs e o microcontrolador (89C51) só tem 2 contadores, foi posta de parte esta hipótese. No caso do trabalho referente ao Robô Minimalista foi utilizado um circuito integrado já com a função de PWM (GL494), em que as características se encontram em anexo.



Figura 3. 1 - Circuito PWM

3.1.2 Controlo do sentido de rotação Para controlo do sentido de rotação dos motores do balão vai utilizar-se um descodificador de 1 bit (Figura 3.2), cuja implementação é feita através de duas portas AND e uma NOT.

Figura 3. 2 - Circuito descodificador



Ponte em H 3.1.3 Uma solução para comandar os motores a partir de sinais lógicas (de baixa energia) é a utilização de um transístor, mas esta solução não permite mudar o sentido de rotação dos motores. A solução encontrada foi a utilização de uma ponte H. Esta montagem permite que se possa mudar o sentido de rotação. Outra vantagem é que permite separar a tensão de alimentação do circuito com a tensão de alimentação dos motores. Podia-se ter implementado o circuito da Figura 3.3 mas optou-se por utilizar um circuito integrado com as mesmas características (L293E) cujas características podem-se ver nos anexos .

Figura 3. 3 - Ponte H



3.1.4 CPLD

3.2 SENSORES

3.2.1

Outro dos problemas encontrados na implementação da lógica de controlo dos motores foi o elevado número de bits necessários para o controlo dos mesmos, já que, para cada motor seriam necessários 5 bits (4 bits de controlo de velocidade e 1 bit de controlo do sentido de rotação), ter-se-ia um total de 15 bits. Como tal, para resolver este problema optou-se por uma implementação de uma interface série através da utilização de um registo de 15 bits. Tendo assim necessidade da utilização de apenas 2 bits: 1 bit para os dados e outro bit (Clk) para o controlo dos mesmos. Para que a implementação de todo o circuito de controlo não se tornasse muito extensa no que diz respeito ao número de integrados, optou-se por utilizar um circuito de lógica programável, nomeadamente uma CPLD (XC9536PC44).

Os sensores são os elementos chave de qualquer sistema de robótica. Estes providenciam o único método de medida das condições envolventes do meio. Os sensores podem medir vários tipos de informação, tal como a intensidade da luz, a temperatura, a pressão, etc. A informação mais importante para um sistema de robótica móvel é a sua proximidade em relação aos objectos. Esta informação é vital para o sistema cumprir as tarefas de navegação evitando os objectos.

SENSOR DE MEDIÇÃO DE DISTÂNCIAS O sensor de distância que se utilizou foi o sensor de infravermelhos. Os critérios que levaram à escolha deste sensor foram as distâncias que este podia medir. Este mede distancias que vão desde 20cm a 150cm. Outro dos critérios que favoreceram a escolha do sensor foi o seu baixo consumo de corrente e a pouca influência à cor dos objectos. O sensor utilizado para a medição de distâncias foi o sensor da marca SHARP com o modelo GP2Y0A02YK (Figura 3.4).



Figura 3. 4 - Sensor de infravermelhos

A técnica de medição utilizada pelo sensor GP2. é denominada por triangulação. Neste processo, uma luz é emitida pelo sensor, sendo reflectida pelo seu alvo para por ultimo ser recebida novamente pelo sensor. Existem três pontos envolvidos, o emissor, o ponto de reflexão e o receptor. A disposição dos pontos formam um triângulo, daí o seu nome.

3.2.1.1. Caracterização do Sensor

Distância do Sensor a um objecto

00,25

0,50,75

11,25

1,51,75

22,25

2,52,75

3

2 6 10 14 18 30 50 70 90 110 130 150Distância (cm)

Ten

são

(Vol

ts) Folha branca

Caderno cinzentoCaderno vermelhoPlastico preto

Figura 3. 5 - Caracterização do sensor relativamente a objectos de diferentes cores

Como se pode ver pela análise da Figura 3.5 o sensor vai ter pouca influência à cor. Um dos problemas deste sensor é que a partir de uma determinada distância o sensor repetirá os valores de outras distâncias, ou seja, vai ter dois valores iguais de saída para distâncias diferentes. Logo, optou-se não utilizar o sensor para distâncias inferiores a 20 cm.



3.3. ADCs Hoje em dia exige-se frequentemente que os dados extraídos num sistema físico sejam convertidos na forma digital. Normalmente estes dados aparecem sob a forma analógica de natureza eléctrica. Surge portanto a necessidade de um dispositivo que converta a informação analógica na forma digital. Foram inventados vários dispositivos deste tipo. Os 4 sistemas mais conhecidos são: 1 - ADC de contagem 2 - ADC de aproximações sucessivas 3 - ADC de comparadores em paralelo ou Flash 4 - ADC de dupla rampa. O ADC é um componente com uma entrada analógica e uma saída digital de n bits. Em relação ao Interface pode-se ter ADCs Série ou Paralelo (Figura 3.6).

Figura 3. 6 – Tipo de ADCs quanto ao Interface



O ADC apresenta um número binário na saída que corresponde ao valor da tensão de entrada (Figura 3.7).

Figura 3. 7 – Resposta Característica do ADC

Tem-se que:

O número de bits na saída, n, denomina-se número de bits do ADC. •

•

•

O número de intervalos de quantificação é n2A resolução do conversor, R, é definida da seguinte forma:

nMaxA

R2

=

−MAXA Gama de tensão de entrada do ADC

n – Número de bits do ADC O último parâmetro associado aos ADCs é a sua velocidade de operação. Devido a não ser exigida uma grande velocidade de operação, nem uma resolução muito elevada, no optou-se por utilizar o MAX1112 que tem as seguintes características:

ADC de Aproximações Sucessivas; •

•

•

•

Número de bits = 8; Interface Série; Número de Canais = 8;



Resolução do ADC utilizado:

VR 016,02096.4

8 ==

De notar que se optou por um ADC de interface série, apenas com o intuito de se utilizar menos linhas de dados para realizar a interface. A escolha do ADC de 8 canais assentou em possíveis melhorias que se possam fazer ao projecto, nomeadamente um acréscimo de sensores. O ADC utilizado requer 4 pinos para Controlo e um pino para Dados. Para realizar a interface entre o ADC e o microcontrolador definiram-se 5 pinos de um dos portos do Microcontrolador para realizar o controlo. Como pinos de controlo do ADC tem-se o CS, SCLK, DIN, SSTRB. O pino de Dados é designado por DOUT. Na Figura 3.8 pode ver-se o diagrama temporal de um ciclo de conversão do ADC.

Figura 3. 8 – Ciclo de conversão do ADC (MAX1112)

O pino DIN é utilizado para programar o ADC. Este pino tem as seguintes funções:

permite escolher se a tensão de referência é interna ou externa; •

•

•

•

o canal do ADC que se pretende ler; o tipo de conversão (unipolar ou bipolar); o tipo de Clock (interno ou externo).



3.4. FOTOTRANSÍSTORES

Figura 3. 9 – Fototransistor

De seguida irão ser descritas algumas das características principais dos fototransístores:

Resposta Espectral • A saída de um fototransistor depende do comprimento de onda da luz incidente. Estes componentes respondem a uma luz que se encontre num intervalo de comprimento de onda caracterizado pelos UVs (ultravioletas), passando pela luz visível, acabando nos IR (infravermelhos).

Figura 3. 10 - Resposta do fototransistor face às diferentes cores

Como se pode observar na Figura 3.10, os fototransístores tanto respondem a luz fluorescente como a luz incandescente, mas o seu comportamento é tanto mais perfeito quando é estimulado por uma luz IR (infravermelha).

Sensibilidade • Para um dado nível de iluminação de uma fonte de luz, a saída de um fototransístor é definida pela área da junção colector-base e pelo ganho em corrente DC do transístor.



A junção colector-base do fototransístor funciona como um foto-díodo, que cria uma foto-corrente que é alimentada na secção da base do transístor. Esta corrente (Ip) depois é amplificada pelo ganho de corrente do transístor. No caso onde não é aplicada externamente nenhuma corrente na base, tem- se: IC = hFE (IP) onde: IC – Corrente no colector hFE – Ganho em corrente dc IP – Foto-corrente A Figura seguinte ilustra o circuito Prático utilizado para a implementação do Fototransistor:

Figura 3. 11 - Circuito implementado para o Fototransistor



3.5. LDRs

Figura 3. 12 - LDR

Como o próprio nome indica, as LDRs (Light dependent resistors) são resistências variáveis com a luz visível. Como se pode observar na Figura 3.12, a LDR é composto por uma linha em zigzag de cor castanha. De acordo com o nível de luz que incide nessa linha, a resistência aumenta ou decresce. A resistência das LDRs tem o seu valor máximo para situações em que esta se encontra no escuro e tem o seu valor mínimo para ocasiões de muita claridade. A situação descrita caracteriza uma LDR denominada LDR de coeficiente negativo. Caso o comportamento seja inverso a LDR denomina-se de coeficiente positivo. De modo a usar este dispositivo num circuito simples, inicialmente começou-se por usar um multímetro de modo a medir a corrente que circula no LDR. No entanto, a medição de corrente não se tornou muito útil. Como tal, colocou-se uma resistência em série com a LDR, e mediu-se a tensão na LDR. Com esta montagem realizou-se um divisor de tensão, sendo a tensão no LDR proporcional à corrente. As figuras que se seguem mostram o conceito descrito.

Figura 3. 13 - Ligação do LDR



Como se pode observar na Figura 3.13, a corrente é proporcional à resistência do LDR.

Figura 3. 14 - Circuito implementado para medir a tensão no LDR

Sendo assim, tem- se que:

VRR

RVLDRLDR

LDR

+=

Tendo em conta que R utilizado anda na ordem das centenas de Ω e o valor máximo da

resistência no LDR é da ordem das dezenas de MΩ, tem-se 1_

_ ≈+ RR

R

MAXLDR

MAXLDR =>

. VVLDR ≈

De acordo com a análise feita ao circuito da Figura 3.14, tem-se que para zonas de muita claridade a tensão V é máxima , sendo praticamente nula para zonas escuras. LDR



3.6. ALIMENTAÇÃO

Figura 3. 15 - Bateria (Idêntica à utilizada)

Não foram realizados testes práticos no que diz respeito a possíveis baterias que satisfizessem as necessidades do sistema. No entanto, foi feita uma consulta que se baseou nos vários tipos de baterias existentes no mercado e que assentou nas relações entre os seguintes termos:

Energia fornecida (mAh) •

•

•

Tensão fornecida (Volts) Peso da bateria (gramas)

As baterias NiMH e as baterias NiCd apresentam algumas semelhanças. No entanto as primeiras apresentam algumas vantagens. As vantagens são a energia fornecida e o tempo de vida. No entanto ambas apresentam uma desvantagem que diz respeito à relação peso/ energia. Sendo a tensão mínima necessária para o sistema funcionar aproximadamente 3,8V, ir-se-ia necessitar logicamente de uma bateria com um valor maior ou igual a este. O problema surge em adquirir uma bateria com esta tensão, com uma capacidade que satisfaça as necessidades do sistema e com um peso máximo de 20g. Devido ao baixo peso permitido para a alimentação recorreu-se ao uso de uma bateria de Li-Ion que apresenta as características pretendidas e que foi fácil adquirir A bateria utilizada é uma bateria de um telemóvel com as seguintes características:

− Tensão Nominal = 3,6V; − Capacidade na ordem dos 820mAh; − Peso = 18g.



4. Experiências

4.1.

4.1.1

Controlo de Altitude A experiência consiste em estabilizar o balão a uma dada distância do tecto (PP), utilizando um sensor de distancia colocado no topo do balão e apontando para o tecto. A experiência reporta resultados com um controlador proporcional (P) e um controlador proporcional-derivativo (PD). Esta experiência começa com uma apresentação teórica deste tipo de controlo.

Controlo em malha fechada Um controlador em malha fechada e um dispositivo que realiza determinados cálculos de modo a conduzir o sistema para uma situação desejada. Uma medida do afastamento entre a saída actual (r) do sistema e a situação desejada (d) e avaliada através de e=r-d, que se denomina o erro da saída. O controlador avalia então o valor a aplicar ao sistema (neste caso os motores) de modo a que este estabilize na posição desejada. A saída do controlador denomina-se acção de controlo. Existem três tipos de acções de controlo:

− Acção proporcional − Acção integral − Acção derivativa

Com a combinação destas acções podemos gerar um sinal de controlo, que se pode chamar por controlo PID, que é genericamente representado por :

∫ ++=t

dttdeTdde

TitKpetu

0

)()(1)()( ττ



4.1.1.1. Acção proporcional Na acção proporcional o sinal de controlo vai ser proporcional à amplitude do valor do erro.

)()(

)()(

trdte

teKptu

−=

×=

,onde, Kp – ganho constante e(t) – diferença entre a distância final e a distância actual d – distância pretendida entre o sensor e a parede que se deve encontrar no final deste controlo Ps(t) – distância medida entre o sensor e o tecto Esta acção consiste essencialmente num amplificador com ganho ajustável.

Sentido do controlo u(t)<0

Sentido do controlo u(t)

Figura 4. 1 - Controlo proporcional

Note-se que, quanto maior o ganho Kp menor o erro em regimmelhor a precisão do sistema em malha fechada. Este erro podeaumento do ganho, entretanto nunca conseguiremos anular compoutro lado, quanto maior o ganho, mais oscilatório tende a fitransitório do sistema em malha fechada. Na maioria dos procesexcessivo do ganho proporcional pode levar o sistema a instabilida

Instituto Politécnico de Setúbal

PE

Sensor

e(t) < 0

> 0
Sensor
e(t) > 0

e permanente, isto é, ser diminuído com o letamente o erro. Por car o comportamento sos físicos, o aumento de.

28


4.1.1.2. Acção Integral Na acção Integral o valor de controlo depende do integral do erro.

∫= dtteTi

tu )(1)(

Ti (tempo integral) é o tempo necessário para que a contribuição da acção integral iguale a da acção proporcional, onde :

TiKi 1

=

A acção integral tem assim uma função "armazenadora de energia". A acção integral está então directamente ligada à melhoria da precisão do sistema. Se, por um lado, a acção integral elimina o erro estacionário, por outro, aumenta o tempo de estabelecimento e piora a estabilidade relativa, o que usualmente é indesejável. Como consequência, o ganho da acção proporcional deve ser reduzido, sempre que esta esteja combinada com a acção integral.

Figura 4. 2 - Controlo Integral



4.1.1.3. Acção Derivativa Na acção Derivativa o sinal de controlo depende da taxa de variação do erro.

dttdeTdtu )()( =

Td (tempo derivativo) é o período de tempo antecipado pela acção relativamente à acção proporcional. Este tipo de controlo tem justamente a função de "antecipar" a acção de controlo a fim de o processo reaja mais rapidamente A adição do modo derivativo ao modo proporcional resulta num controlador altamente sensível, uma vez que o primeiro, ao responder a uma taxa de variação do erro, permite correcções antes deste ser elevado. Não obstante o modo derivativo não afectar directamente o erro estacionário, adiciona amortecimento ao sistema (melhora a estabilidade) e assim permite o uso de valores de Kp mais elevados, o que implica um menor erro estacionário. Um inconveniente deste modo é o de acentuar o ruído de alta frequência.

Figura 4. 3 - Controlo Derivativo

Logo a forma final do PID será dada por:

( )

×+×+×= ∫ dt

tdeKddtteKiteKptu )()()()(



4.1.2 Software de Controlo De modo a realizar o controlo do dirigível, foi desenvolvida uma aplicação em Visual Basic, cujo código é apresentado em ANEXOS (ANEXOS 1). Esta aplicação é constituída apenas por uma janela (Figura xx) que apresenta as seguintes funções:

• Iniciar e terminar o processo de controlo; • Visualizar os valores do sensor; • Visualizar a velocidade do motor; • Ajustar os ganhos (Kp, Kd e Ki).

Figura 4. 4 – Janela do Software realizado



4.1.3 Resultados Os testes efectuados para cada controlador vão ter como ponto de referência o ponto de estabilidade do balão. O primeiro teste consiste em variar o ganho da constante proporcional anular os restantes ganhos, ou seja, implementa-se, controlo proporcional (P).

0

0,1

0,2

0,3

0,4

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1 23 45 67 89 111

133

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485

507

Amostra 1Amostra 2

Figura 4. 5 - Controlo proporcional com Kp = 5

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0,9

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Amostra 1Amostra 2




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Amostra 1Amostra 2


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529

Amostra 1Amostra 2

Figura 4. 8 - - Controlo proporcional com Kp = 20

Analisando os gráficos, verifica-se que com o aumento de Kp a sobreelevação e o tempo de estabelecimento aumenta, sendo que quanto mais aumentamos Kp mais o sistema tende a ficar instável. Por sua vez quanto menor for Kp mais suave vai ser o nosso controlador.



Agora analisa-se o controlador do tipo PD (controlador proporcional derivativo)

0

0,1

0,2

0,3

0,4

0,5

0,6

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0,8

0,9

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Amostra 1Amostra 2

Figura 4. 9 - Controlo Pd com Kd = 5

0

0 ,1

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1

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A m o s tr a 1A m o s tr a 2




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Amostra 1Amostra 2


Analisando os gráficos ,verifica-se que com o aumento de Kd a sobreelevação e o tempo de estabelecimento vai aumentar.



Por último, testa-se o controlador do tipo Pi (controlador proporcional integral).

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

11 12 23 34 45 56 67 78 89 100

111

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Amostra 1Amostra 2

Figura 4. 12 - Controlo Pi com Ki = 1

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Amostra 1Amostra 2




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A m o s tra 1A m o s tra 2


Como se pode observar pelas Figuras 4.12, 4.13, 4.14, este controlador aumenta a instabilidade do nosso sistema, pois quando se aumenta o ganho o sistema tende a ficar instável. Fazendo agora a comparação do controlador P com o PI e PD o que se verifica é que para o controlador PI em relação ao P é que o PI vai ter uma sobreelevação maior e uma frequência de oscilação também superior mas um tempo de estabelecimento inferior, em relação aos P com o PD não se conseguiu concluir muito devida as várias interferências que surgiram, onde um dos problemas é a variação do teste do ponto de estabilidade, devido a fugas de hélio do balão, pois no final de uma hora a referencia variava bastante, como se pode ver nas figuras 4.15 e Figura 4.16, onde na Figura 4.15 o valor médio da referencia vai ser de ±0.72V e em 4.16 é de 0.53V



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A m o s t ra 1A m o s t ra 2

Figura 4. 15 – Gráfico de altitude do balão com fios

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Amostra 1Amostra 2

Figura 4. 16 – Gráfico de altitude do balão com fios passado uma hora



4.2 Robot Minimalista O Robot Minimalista é caracterizado por ter ligações directas dos sensores aos motores. A atribuição do nome ao Robot assentou precisamente na sua simplicidade. A experiência consiste em projectar um Robot que tem a capacidade de se deslocar de zonas de maior claridade para zonas de menor claridade (escuro). Para detectar a variação do nível de luz foram utilizados duas LDRs. As LDRs encontram-se acopladas na parte da frente do Cockpit do Dirigível. De notar que as LDRs foram dispostas no cockpit do dirigível formando um ângulo de 45º em relação a um eixo longitudinal, como se pode observar na Figura 4.17. A disposição escolhida para as LDRs foi implementada deste modo com o intuito de apresentar um campo de visão o mais alargado possível, relativamente ao seu sentido de deslocamento.

Figura 4. 17 – Cockpit do Dirigível com os LDRs e o Fototransistor acoplados



O LDR do lado direito do cockpit do Dirigível encontra-se ligado ao motor do lado direito do dirigível e vice versa. No caso da ligação dos motores às LDRs fosse cruzada (o motor do lado direito fosse ligado ao LDR do lado esquerdo e vice-versa) o dirigível em vez de se afastar das zonas de claridade, iria dirigir-se para as zonas de maior claridade. O PWM utilizado para o controlo da velocidade dos motores é gerado por um circuito integrado (referido anteriormente) que tem capacidade de controlar o duty cycle (largura do pulso) dos 50% (Figura 4.18) aos 100%. Sendo assim considerou-se que quando as LDRs estão a detectar um nível de luminosidade inferior ao nível de referencia, ambos os motores se encontram a funcionar a uma dada velocidade. Sendo assim, tem-se que o balão está sempre em movimento.

Figura 4. 18 – Sinal à saída do circuito do PWM para um nível de luminosidade inferior ao valor de

referencia No caso da LDR do lado direito (*), ao detectar um nível de luminosidade superior ao valor de luminosidade de referência, a tensão à entrada do PWM aumentará, o que provocará um aumento da largura do pulso à saída, incrementando assim a velocidade do motor do lado direito (Figura 4.19).

(* )Nota : Quando se fala do lado direito do cokpit do Dirigível, está a ser referido o lado esquerdo das Figuras 4.17 e 4.19, visto a imagem ser de uma perspectiva da vista de baixo do cokpit.



Ao aumentar a velocidade do motor do lado direito o dirigível irá começar a virar para o lado esquerdo afastando-se assim da zona de maior luminosidade (Figura 4.19). Pelo mesmo processo, um aumento do nível de luminosidade na outra LDR faz com que o balão curve para a direita.

Figura 4. 19 – Foco de luz a incidir sobre o LDR do lado direito do cokpit do balão

Para além das LDRs foi também utilizado um fototransístor que tem como função controlar o motor que controla a altitude do dirigível. Como o balão é um sistema estável por não necessitar da actuação de motores para se manter no ar a uma dada altitude, implica que o motor de controlo de altitude, ao contrário dos outros motores não se encontra sempre a funcionar. Não se encontrando sempre a funcionar, a utilização do motor de altitude é necessária quando se pretende que o dirigível aumente a sua altitude ou no caso de este se encontrar a voar à muito tempo, é necessário compensar a perda de altitude que ocorre devido às fugas de hélio. De modo a colocar o motor a funcionar incide-se uma luz sobre o fototransístor através de uma lanterna vulgar (Figura 4.20). A intensidade da luz no fototransístor vai determinar se a polarização da base é suficiente para o fototransistor entrar em condução provocando o funcionamento do motor.



Figura 4. 20 – Foco de luz a incidir sobre o Fototransistor

Na tabela seguinte (Tabela 4.1) é possível observar o peso de todos os componentes que foram utilizados para implementar o Robot Minimalista. Como se pode observar, a electrónica constituinte e a alimentação fazem um total de aproximadamente 34 gramas. Que somado ao peso do balão com cockpit é inferior a 78 gramas.

Material Quantidade Peso (Unidade) Peso Ics 3X 0.99 g 3,97 g Resistências 5X 0,16 g 0,80 g Potenciómetros 2X 0,39 g 0,78 g LDRs 2X 0.17 g 0,34 g Fototransístores 1X 0.19 g 0,19 g Díodos 1X 0,20 g 0,20 g Condensadores 2X 0,14 g 0,28 g Conectores 12X 0,07 g 0,84 g Placa PCB 1X 5,40 g 7,00 g TOTAL1 = Electrónica + Placa PCB - - 14,50 g Alimentação (Bateria) 1X 20 g 19 g TOTAL2 = TOTAL1 + Alimentação - - 33,5 g Cockpit 1X 40 g 42 g TOTAL 75,5 g

Tabela 4. 1 – Peso de todos os componentes utilizados no Robot Minimalista



5.

5.1 Conclusões

Conclusões e Perspectivas de Trabalho Futuro

Este projecto contribuiu para a aquisição de conhecimentos relativos ao funcionamento de diversos sensores ópticos que existem no mercado. O conhecimento alargou-se aos sensores que foram utilizados nos trabalhos, nomeadamente as LDRs, os fototransístores e os sensores de infravermelhos de medição de distâncias. Tomou-se também um conhecimento mais alargado do funcionamento dos motores de corrente contínua no que diz respeito ao seu controlo e interface com um controlador. De referir o importante desenvolvimento de conhecimentos relativos à área de controlo de sistemas, mais especificamente a implementação de controladores P, PD e PI que foram vocacionados no nosso caso para o controlo de um balão a hélio. De salientar algumas semelhanças entre o nosso projecto e um projecto de licenciatura de um aluno Suíço, denominado “Evolutionary Blimp”. O seu objectivo assentou na construção de um dirigível autónomo que tivesse a capacidade de circular livremente num local fechado. O dirigível é constituído por 3 motores, 6 detectores de obstáculos e 2 câmaras de imagem. Este trabalho teve como resultados a obtenção de um Dirigível que tem a capacidade de se deslocar num local fechado desviando-se de objectos. Como se observou, em termos genéricos, o objectivo do trabalho do aluno Suíço é idêntico ao nosso. As diferenças assentam no controlador implementado. Há que referir que implementar um controlador do tipo do “Evolutionary Blimp” torna-se mais simples comparando com o controlador implementado no nosso trabalho. De notar que a principal dificuldade encontrada na utilização de dirigíveis é o seu ponto de estabilidade. Visto o “Evolutionary Blimp” se encontrar permanentemente em deslocação não se coloca o problema da estabilidade do balão. Ou seja, é mais fácil controlar os movimentos de um dirigível em movimento do que controlar a ausência de movimentos.



5.2 Futuros desenvolvimentos

O trabalho descrito neste projecto, abre, no entender dos autores, diversas perspectivas no que diz respeito à realização do projecto, de acordo com os requisitos que eram propostos inicialmente, tal como a introdução de possíveis módulos. Para a realização dos requisitos iniciais do projecto, teria inicialmente que conceber-se um balão que suportasse aproximadamente o dobro do peso suportado pelo balão utilizado. Um desenvolvimento futuro poderia passar pela implementação de uma câmara digital que desempenhasse funções de vigilância. Outra das implementações passaria pela introdução de um módulo RF ou de um módulo Bluetooth. Esses módulos iriam favorecer o sistema na medida que se poderia utilizar electrónica fora do dirigível. Isso permitiria que o peso total do balão não aumentasse com o aumento da complexidade do controlador. Este seria implementado num PC, com todas as facilidades que daí adviriam.



Referências Bibliográficas [1] Sedra Smith, “Microelectronic Circuits”, Fourth Edition, Oxford, 1998 [2] Steven Holzner, “Visual Basic 6 Black Book”, The Coriolis Group, 1998 [3] http://users.pandora.be/educypedia/electronics/sensorsoptical.htm [4] http://www.draganfly.com [5] http://www.gasin.pt/index.htm [6] http://student.dee.uc.pt/~jalmeida/index_files/5.htm [7] http://www.delet.ufrgs.br/~jmgomes/pid/Apostila/apostila/node24.html [8] www.wizard.org_schem_motor.html


ANEXOS

ANEXOS

i

ANEXOS

Índice ANEXOS 1 ........................................................................................................................ iii

Listagem da Programação do Microcontrolador............................................................ iv Listagem Da Programação Do Software de Controlo.................................................. xiii

ANEXOS 2 ....................................................................................................................... xx Esquemático do 1º Trabalho ....................................................................................... xxi Esquemático do 2º Trabalho ...................................................................................... xxiii PCB do 1º Trabalho .................................................................................................... xxv PCB do 2º Trabalho .................................................................................................. xxvii Esquemático da lógica implementada na CPLD........................................................ xxix

ANEXOS 3 .................................................................................................................. xxxiv GP2Y0A02YK.......................................................................................................... xxxv L78xx ............................................................................................................................. xl 1N4001......................................................................................................................... lxv GL494 ....................................................................................................................... lxviii L293 .......................................................................................................................... lxxvi MAX1112 ............................................................................................................. cxxxvii MAX233 ............................................................................................................... cxxxvii HEF4047 ................................................................................................................. clxxiv AT89C51......................................................................................................................cxc XC9536PC44 ........................................................................................................... ccviii

ANEXOS 4 ..................................................................................................................ccxvii Lista do material implementado............................................................................. ccxviii

ii

ANEXOS 1 – Listagem do Código de Programação

ANEXOS 1

iii


Listagem da Programação do

Microcontrolador

iv

$mod51 ; identificador que permite o compilador do microcontrolador ; utilizado reconhecer as instruções deste ; ******************************** ; * ATRIBUIÇAO DOS BITS DE * ; * CONTROLO DO DAC A * ; * PORTOS DO MICRO * ; * * ; * P1.4 = Cont_bits * ; * P1.5 = I0 * ; ******************************** LETRAENVIA DATA 70H VALOR0 DATA 71H VALOR1 DATA 74H VALOR2 DATA 75H sentido0 data 76h sentido1 data 77h sentido2 data 78h LIXO DATA 2FH HIGH_BITS data 73H escolha data 69h ValorDAC DATA 32H MOV R2,#00h SETB P1.7 ORG 0000H ; Espaco de memoria de programa alocado para o inicio do programa LJMP MAIN ; O salto para a main do programa ; memoria depois da instrução ORG, logo torna-se necessario fazer um ; salto para um procedimento que vá executar o programa. ;********************************************************************************* ;************PROCEDIMENTO QUE RECEBE VALORES DA PORTA SÉRIE************** ;********************************************************************************* ORG 0023H jb ri,label1 ; salta a a label 1 quando receber algum caracter reti label1: clr ri ; rotina para receber um caracter mov a,sbuf MOV LETRAENVIA,a ACALL verifi reti ;********************************************************************** ;************PROCEDIMENTO QUE RECEBE BITS DO ADC**************** ;********************************************************************** RECEBER_ADC: ; Inicialização do ADC

SETB P1.1 ; Colocar CS a HIGH CLR P1.0 ; Colocar SCLK a LOW CLR P1.2 ; Colocar DIN a LOW CLR P1.1 ; Colocar CS a LOW NOP SETB P1.2 ; Colocar DIN a HIGH (BIT - START) SETB P1.0 ; Colocar SCLK a HIGH NOP ; ///// CLOCK ////// CLR P1.0 ; Colocar SCLK a LOW MOV R3,#01H ; Registo auxiliar MOV R1,#03H ; Contador dos CANAL que se pretende ler LERCANAL: MOV A,R2 ; R2 Contem o valor do canal que se pretende ler ANL A,R3 JZ ENVIAZERO SETB P1.2 ; Envio dos bits do CANAL (SEL2,SEL1,SEL0) ENVIAR: SETB P1.0 ; Colocar SCLK a HIGH NOP ; ///// CLOCK ////// CLR P1.0 ; Colocar SCLK a LOW MOV A,R3 RL A ; Roda para a esquerda o acum. para comparar o bit seguinte do CANAL MOV R3,A DEC R1 ; Decrementa o contador de bits do CANAL MOV A,R1 JZ FIMCANAL ; Ja foram enviados os 3 Bits de escolha do CANAL a ler JMP LERCANAL ; Ainda nao foram enviados todos os bits referentes ao CANAL ENVIAZERO: CLR P1.2 JMP ENVIAR FIMCANAL: SETB P1.2 ; Colocar DIN a HIGH para ENVIAR bits UNI,SGL,PD1 e PD0 MOV R4,#04H CONTINUA: SETB P1.0 ; Colocar SCLK a HIGH

NOP ; ///// CLOCK ////// CLR P1.0 ; Colocar SCLK a LOW DEC R4 MOV A,R4 JZ RECEBE_VALOR ; salta para RECEBE_VALOR para receber o valor que se encontra no CANAL JMP CONTINUA RECEBE_VALOR: CLR P1.2 MOV R7,#07H SETB P1.0 NOP CLR P1.0 NOP NOP NOP CONTINUALER: SETB P1.0 NOP CLR P1.0 ; LEITURA DO VALOR PARA O MICRO JB P1.3, ValorUM JMP ValorZERO ValorUM: MOV A,ValorDAC ADD A,#01H RL A MOV ValorDAC,A MOV A,R7 DEC R7 MOV A,R7 JZ FIM_ADC JMP CONTINUALER ValorZERO: MOV A,ValorDAC ADD A,#00H RL A MOV ValorDAC,A DEC R7 MOV A,R7 JZ FIM_ADC

JMP CONTINUALER FIM_ADC: JB P1.3, ValorUM_ JMP ValorZERO_ ValorUM_: MOV A,ValorDAC ADD A,#01H MOV ValorDAC,A JMP FIM_ADC_ ValorZERO_: MOV A,ValorDAC ADD A,#00H MOV ValorDAC,A FIM_ADC_: MOV R6,#07H RECEBER_ZEROS: SETB P1.0 ; Colocar SCLK a HIGH NOP ; ///// CLOCK ////// CLR P1.0 ; Colocar SCLK a LOW DEC R6 MOV A,R6 JZ FINAL_ADC JMP RECEBER_ZEROS FINAL_ADC: SETB P1.1 ; Coloca CS a HIGH (Termina um Ciclo do ADC) NOP ret ENVIAR_PORTA_SERIE: clr ti MOV A,ValorDAC MOV SBUF,A espera: jnb ti,espera RET ;****************************************************************************** ;*****************PROCEDIMENTO QUE ENVIA BITS PARA O CPLD**************** ;******************************************************************************

CONTINUAENVIO: MOV A,LIXO ANL A,B JZ ZERO SETB P1.5 JMP ENVIAR_BIT_pal ZERO: CLR P1.5 ; Coloca o bit I0 com o valor lógico 0 ; De seguida vai-se enviar o bit que se encontra em I0 para a CPLD ENVIAR_BIT_pal: clr p1.4 NOP NOP NOP NOP setb P1.4 DEC R5 ; Decrementa o valor de R5, pois foi enviado um bit, ou mais um bit MOV A,R5 ; Move o valor de R5 para o acumulador JZ TERMINOU_ENVIO_ ; Se acumulador for 0 salta para a label TERMINOU_ENVIO, o que ; significa que já foram enviados os 5 bits MOV A,B ; Estas operações efectuam um conjunto de instruções que carregam MOV B,#02H ; o Registo B com um valor que irá permitir detectar qual o nivel lógico div AB ; do bit seguinet que se irá enviar para a CPLD mov B,A JMP CONTINUAENVIO ; Salta para a label CONTINUAENVIO para efectuar as operações que ; permitem detectar o nível lógico do bit seguinte a enviar. TERMINOU_ENVIO_: RET ; retorna ao programa e coloca o program counter com o valor da ; posição de memoria a seguir à qual se encontrava a chamada ao ; procedimento CONTINUAENVIO para continuar o programa ;****************************************************************************** ;*****************PROCEDIMENTO QUE ENVIA BITS PARA A CPLD********************** ;****************************************************************************** ; Para enviar bits para a cpld são necessárias um conjunto de instruções que passam ; pelo configuração dos pinos de controlo deste. ; Instruções estas que se encontram descritas a seguir. ENVIAMOTOR: MOV LIXO,VALOR2 MOV R5,#05d ; Registo que funciona como contador do número de bits a enviar para a CPLD MOV B,#16d ; O Registo B funciona como um registo auxiliar para calculos Acall continuaenvio

MOV LIXO,VALOR1 MOV R5,#05d ; Registo que funciona como contador do número de bits a enviar para a CPLD MOV B,#16d ; O Registo B funciona como um registo auxiliar para calculos Acall continuaenvio MOV LIXO,VALOR0 MOV R5,#05d ; Registo que funciona como contador do número de bits a enviar para a CPLD MOV B,#16d ; O Registo B funciona como um registo auxiliar para calculos Acall continuaenvio ret ;****************************************************************************** ;*******PROCEDIMENTO QUE VERIFICA QUAL O CONTROLO A FAZER************* ;****************************************************************************** verifi : mov a, letraenvia ; verifica se é para enviar para o adc mov b, #10000000b anl a,b jz motor mov a, letraenvia mov b, #01111111b anl a,b mov R2,a jmp main_ motor: mov a, letraenvia ; verifica se é para enviar informaçao para o motor 0 mov b, #01100000b anl a,b cjne a,#96,motor1 mov a, letraenvia mov b, #00011111b anl a,b mov Valor2,a acall enviamotor jmp final motor1: cjne a,#64,motor0 mov a, letraenvia ; verifica se é para enviar informaçao para o motor 1 mov b, #00011111b anl a,b mov Valor1,a acall enviamotor jmp final motor0: cjne a,#32,motor1 mov a, letraenvia ; verifica se é para enviar informaçao para o motor 2 mov b, #00011111b anl a,b mov Valor0,a acall enviamotor final: ret

;**************************************************************** ; INICIAR A PORTA SERIE ;**************************************************************** INIC_SERIE: mov tmod,#20h ; 00100000 ; B7 a B4 - pertencem ao timer 1 GATE C/T M1 M0 (0010) ; Gate = 0 (temporizador 1 est enable quando o bit de controlo Trx = 1) ; C/T ; M1 M0 - 10 (Modo de opera‡ao - Temporizador/Contador de 8 bits c/ autoReload. ; TH1 contem o valor de reload) ; B3 a B0 - pertencem ao timer 0 (B3 a B0 = 0) (0000) mov th1,#0fah ; 0fd(253) - para BD - 19200 b/s ; 0fa(250) - BD = 4800 b/s mov tcon,#00h ; Limpa o Registo TCON mov scon,#50h ; 01010000 ; 01010000 = SM0 SM1 SM2 REN TB RB8 TI RI ; 01 = SMO SM1 - Modo Funcionamento 1 ; TB e RB8 = 0, So sao utilizados no modo 2 e 3 ; TI e RI = 0, Sao activados no decorrer do programa ; caso se esteja a enviar ou a receber dados. setb tr1 ;setb ti ; ti=1 para ENVIAR bit pela porta série mov ie,#90h ; EA=0 Disable todas as interrup‡äes e ; ES liga ou desliga as interrup‡oes da porta serie mov pcon,#00h ; Pcon = 0, pois nao ‚ nessec rio duplicar a Baud Rate ; Limpa o registo PCON ret ;********************************************************************************** ;*****SUB_PROCEDIMENTO MAIN (PROCEDIMENTO SECUNDÁRIO)******************** ;********************************************************************************** MAIN_: MOV ValorDAC,#00H ACALL RECEBER_ADC ACALL ENVIAR_PORTA_SERIE RET

;********************************************************************************** ;************PROCEDIMENTO MAIN (PROCEDIMENTO PRINCIPAL)******************** ;********************************************************************************** MAIN: setb p1.4 ACALL INIC_SERIE MOV VALOR0,#00H MOV VALOR1,#00H MOV VALOR2,#00H ma: jmp ma END ; Label de Fim de programa


Listagem Da Programação Do

Software de Controlo

xiii

Dim recebeu As Boolean Dim buffer() As Byte Dim inicio As Boolean Dim espera As Boolean Dim fimciclo As Boolean Dim KP As Integer Dim KD As Integer Dim KI As Integer Dim Veloc3 As Integer Dim ValorSensor As Double Dim Valorref As Double Dim CP As Double Dim CD As Double Dim CI As Double Private Sub Command1_Click() Dim s As String Dim i As Integer Dim k As Integer Dim j As Integer Dim h As Integer Dim auxvel As Integer Dim MAXSENSORES As Integer Dim MAXAMOSENSORES As Integer Dim MAXAMOSTRAI As Integer Dim AUXSENSORES(2) As Double Dim ValorSensoractual As Double Dim ValorSensorAnterior As Double Dim DifSensor As Double Dim SomaI As Double Dim erro As Double Dim amostra(8) As Double Dim CPID As Double Dim auxvel3 As Byte MAXSENSORES = 0 MAXAMOSENSORES = 15 MAXAMOSTRAI = 4 ValorSensorAnterior = Valorref ' criar um ficheiro com o nome da hora minutos e secundos s = "C:\dados\" & Hour(Now) & Minute(Now) & Second(Now) & ".txt" Open (s) For Output Shared As #1 fimciclo = False Do If fimciclo Then Exit Do End If ' ciclo para receber os valores do sensor For i = 0 To MAXSENSORES AUXSENSORES(i) = 0 For k = 0 To MAXAMOSENSORES

MSComm1.Output = Chr(128) Do If recebeu Then recebeu = False AUXSENSORES(i) = (buffer(0) * 0.01606) + AUXSENSORES(i) Exit Do End If DoEvents Loop Next k ' faz a media do valores dos sensores ValorSensor = Round(AUXSENSORES(i) / MAXAMOSENSORES, 2) ' mostra o valor do sensor Text8.Text = ValorSensor Next i ' guarda o valor do sensor no ficheiro Write #1, ValorSensor, Minute(Now), Second(Now) 'calcula a diferença entre o valor de referencia e o valor do sensor que da o erro erro = Valorref - ValorSensor ' calcula a contribuição proporcional do sistema CP = Round(erro * KP, 2) ' calcula a contribuição do controlador D ValorSensoractual = ValorSensor DifSensor = ValorSensorAnterior - ValorSensoractual ValorSensorAnterior = ValorSensoractual CD = DifSensor * KD ' calcula a contribuição do controlador I If j > MAXAMOSTRAI Then j = 0 End If amostra(j) = erro j = j + 1 For h = 0 To MAXAMOSTRAI SomaI = amostra(h) + SomaI Next h CI = SomaI * KI ' mostra as diferentes contribuições ao controlador Text5.Text = CP Text6.Text = CD Text7.Text = CI CPID = CP + CI - CD SomaI = 0 Text10.Text = Time Text11.Text = CPID If CPID > 8 Then CPID = 8 End If If CPID < -8 Then CPID = -8 End If If CPID = 0 Then Veloc3 = 0 MSComm1.Output = Chr(96) Else ' rotina de envio da velocidade a que os motores devem andar If CPID > 0 Then

If Veloc3 = (Round(CPID, 0) + 7) Then Else MSComm1.Output = Chr(127) Timer1.Interval = 1 Timer1.Enabled = True espera = False Do If espera Then Exit Do End If DoEvents Loop auxvel3 = CByte(Round(CPID)) MSComm1.Output = Chr(auxvel3 + 119) Timer1.Interval = 1 Timer1.Enabled = True espera = False Do If espera Then Exit Do End If DoEvents Loop Veloc3 = auxvel3 + 7 End If Else If Veloc3 = (Round(CPID, 0) - 7) Then Else MSComm1.Output = Chr(111) Timer1.Interval = 1 Timer1.Enabled = True espera = False Do If espera Then Exit Do End If DoEvents Loop auxvel3 = CByte(Round(-CPID)) MSComm1.Output = Chr(auxvel3 + 103) Veloc3 = CPID - 7 Timer1.Interval = 1 Timer1.Enabled = True espera = False Do If espera Then Exit Do End If DoEvents Loop End If End If End If Text4.Text = Veloc3

Timer1.Interval = 500 Timer1.Enabled = True espera = False Do If espera Then Exit Do End If DoEvents Loop DoEvents Loop MSComm1.Output = Chr(96) Timer1.Interval = 5 Timer1.Enabled = True espera = False Do If espera Then Exit Do End If DoEvents Loop Text4.Text = 0 Close #1 End Sub Private Sub Command2_Click() ' final do programa End End Sub Private Sub Command3_Click() fimciclo = True End Sub Private Sub Form_Load() MSComm1.PortOpen = True Text1.Text = KP VScroll1.Value = KP Text2.Text = KD VScroll2.Value = KD Text3.Text = KI VScroll3.Value = KI Text4.Text = Veloc3 HScroll1.Value = Veloc3 End Sub Private Sub HScroll1_Change() Veloc3 = HScroll1.Value Text4.Text = Veloc3 End Sub Private Sub MSComm1_OnComm() Dim sMessage As String ' rotina da porta serie

Select Case MSComm1.CommEvent ' mensagens dos eventos Case comEvReceive buffer() = MSComm1.Input recebeu = True Case comEvSend Case comEvCTS sMessage = "Detectada alteração em CTS" Case comEvDSR sMessage = "Detectada alteração em DSR" Case comEvCD sMessage = "Detectada alteração em CD" Case comEvRing sMessage = "O fone esta tocando" Case comEvEOF sMessage = "Fim de arquivo encontrado" ' Error messages. Case comBreak sMessage = "Break recebido" Case comCDTO sMessage = "Carrier Detect Timeout" Case comCTSTO sMessage = "CTS Timeout" Case comDCB sMessage = "Error retrieving DCB" Case comDSRTO sMessage = "DSR Timeout" Case comFrame sMessage = "Erro - Framing" Case comOverrun sMessage = "Erro - Overrun " Case comRxOver sMessage = "Receive Buffer Overflow" Case comRxParity sMessage = "Erro de Paridade" Case comTxFull sMessage = "Transmite Buffer Cheio" Case Else sMessage = "Erro ou evento desconhecido" End Select 'SetStatus (sMessage), False End Sub Private Sub Text1_Change() KP = Text1.Text VScroll1.Value = KP End Sub Private Sub Text2_Change() KD = Text2.Text VScroll2.Value = KD End Sub

Private Sub Text3_Change() KI = Text3.Text VScroll3.Value = KI End Sub Private Sub Text4_Change() Veloc3 = Text4.Text HScroll1.Value = Veloc3 End Sub Private Sub Text9_Change() Valorref = Text9.Text End Sub Private Sub Timer1_Timer() espera = True End Sub Private Sub VScroll1_Change() KP = VScroll1.Value Text1.Text = KP End Sub Private Sub VScroll2_Change() KD = VScroll2.Value Text2.Text = KD End Sub Private Sub VScroll3_Change() KI = VScroll3.Value Text3.Text = KI End Sub

ANEXOS 2 – Esquemáticos e PCBs

ANEXOS 2

xx


Esquemático do 1º Trabalho

xxi


Esquemático do 2º Trabalho

xxiii


PCB do 1º Trabalho

xxv


PCB do 2º Trabalho

xxvii


Esquemático da lógica implementada

na CPLD

xxix

Circuito Final da CPLD

Bloco da comp_shifd

Bloco Comparador

Bloco Contador

ANEXOS 3 - Fichas Técnicas do Hardware desenvolvido

ANEXOS 3

xxxiv


GP2Y0A02YK

xxxv

GP2Y0A02YK

GP2Y0A02YK

Absolute Maximum Ratings

Recommended Operating Conditions

Outline Dimensions (Unit : mm)

Long Distance Measuring Sensor

Features1. Less influence on the colors of reflected objects and their

reflectivity, due to optical triangle measuring method

2. Distance output type

(Detection range:20 to 150cm)

3. An external control circuit is not necessary

Output can be connected directly to a microcomputer

*1 Open collector output

Parameter Symbol Rating UnitSupply voltage VCC V

Operating temperature Topr −10 to +60 °C−0.3 to VCC +0.3 V

−0.3 to +7Output terminal voltage VO

*1

Storage temperature Tstg −40 to +70 °C

(Ta=25°C)

Notice In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

Internet Internet address for Electronic Components Group http://sharp-world.com/ecg/

Parameter Symbol Rating UnitVCC 4.5 to 5.5 VOperating Supply voltage

1. For detection of human body and various types of objects in

home appliances, OA equipment, etc

Applications

374-R1.75

R3.75

Light emitterside

29.5

4.475

φ3.2

19.8±0.1

φ3.2

R3.75

Light detectorside

4-R1.75

10.1

13 11.9

Lens case

Connector

PWB 3.3

1.2

14.4

14.4

21.6

2-1.

5

4.58.95 10.45

18.9

+0.5

−0.3

1

2

3

VO

GNDVCC

The dimensions marked aredescribed the dimensions oflens center position.

Unspecified tolerance : ±0.3mm

Terminal connection

1 3

GP2Y0A02YK

Electro-optical CharacteristicsParameter Conditions

*2 *3

*2 L=150cm *2 Output change at L=150cm to 20cm

−

(Ta=25°C, VCC=5V)

MIN.

20

0.251.8

−

TYP.

−0.4

2.05

33

MAX.

0.55

150

2.3

50

Unit

cm

V

V

mA

Distance measuring range

Output terminal voltage

Difference of output voltage

Symbol

∆L

VO

∆VO

ICCAverage dissipation currentNote) L:Distance to reflective object*2 Using reflective object:White paper (Made by Kodak Co. Ltd. gray cards R-27 ⋅ white face, reflective ratio;90%)*3 Distance measuring range of the optical sensor system

Fig.1 Internal Block Diagram

Signalprocessing

circuit

LED drive circuit

VCC 5V

VO

GND

PSD

LED

Voltageregulator

Outputcircuit

Oscillationcircuit

Distance measuring IC

Fig.2 Timing Chart

MAX. 5.0ms

38.3ms±9.6ms

VO (Output)

Distancemeasuringoperation

First measurement Secondmeasurement

nthmeasurement

Unstable output First output Second output nth output

VCC

(Power supply)

GP2Y0A02YK

Fig.3 Analog Output Voltage vs. Distance to Reflective Object

Ana

log

outp

ut v

olta

ge (

V)

0

1

2

0.5

1.5

3

2.5

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Distance to reflective object L (cm)

White Reflectivity:90%Gray Reflectivity:18%

NOTICE

The circuit application examples in this publication are provided to explain representative applications of SHARPdevices and are not intended to guarantee any circuit design or license any intellectual property rights. SHARP takesno responsibility for any problems related to any intellectual property right of a third party resulting from the use ofSHARP's devices.

Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. SHARPreserves the right to make changes in the specifications, characteristics, data, materials, structure, and other contentsdescribed herein at any time without notice in order to improve design or reliability. Manufacturing locations arealso subject to change without notice.

Observe the following points when using any devices in this publication. SHARP takes no responsibility for damagecaused by improper use of the devices which does not meet the conditions and absolute maximum ratings to be usedspecified in the relevant specification sheet nor meet the following conditions:

(i) The devices in this publication are designed for use in general electronic equipment designs such as:- - - Personal computers- - - Office automation equipment- - - Telecommunication equipment [terminal]- - - Test and measurement equipment- - - Industrial control- - - Audio visual equipment- - - Consumer electronics

(ii) Measures such as fail-safe function and redundant design should be taken to ensure reliability and safety whenSHARP devices are used for or in connection with equipment that requires higher reliability such as:- - - Transportation control and safety equipment (i.e., aircraft, trains, automobiles, etc.)- - - Traffic signals- - - Gas leakage sensor breakers- - - Alarm equipment- - - Various safety devices, etc.

(iii)SHARP devices shall not be used for or in connection with equipment that requires an extremely high level ofreliability and safety such as:- - - Space applications- - - Telecommunication equipment [trunk lines]- - - Nuclear power control equipment- - - Medical and other life support equipment (e.g., scuba).

Contact a SHARP representative in advance when intending to use SHARP devices for any "specific" applicationsother than those recommended by SHARP or when it is unclear which category mentioned above controls theintended use.

If the SHARP devices listed in this publication fall within the scope of strategic products described in the ForeignExchange and Foreign Trade Control Law of Japan, it is necessary to obtain approval to export such SHARP devices.

This publication is the proprietary product of SHARP and is copyrighted, with all rights reserved. Under the copyrightlaws, no part of this publication may be reproduced or transmitted in any form or by any means, electronic ormechanical, for any purpose, in whole or in part, without the express written permission of SHARP. Express writtenpermission is also required before any use of this publication may be made by a third party.

Contact and consult with a SHARP representative if there are any questions about the contents of this publication.


L78xx

xl

L7800SERIES

January 1993

POSITIVE VOLTAGE REGULATORS

.OUTPUT CURRENT UP TO 1.5A.OUTPUT VOLTAGES OF 5; 5.2; 6; 8; 8.5; 9; 12;15; 18; 20; 24V.THERMAL OVERLOAD PROTECTION.SHORT CIRCUIT PROTECTION.OUTPUT TRANSISTOR SOA PROTECTION

DESCRIPTIONThe L7800 series of three-terminal positive regula-tor is available in TO-220, ISOWATT220 and TO-3packages and with several fixed output voltagesmaking it useful in a wide range of applications.These regulators can provide local on-card regula-tion, eliminating the distribution problems associ-ated with singlepoint regulation. Each type employsinternal current limiting, thermal shut-down and safearea protection, making it essentially indestructible.If adequate heat sinking is provided, theycan deliverover 1A output current. Although designed primarilyas fixed voltage regulators, these devices can beused with external components to obtain adjustablevoltages and currents.

BLOCK DIAGRAM

TO-3

TO-220 ISOWATT220

1/24

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Vi DC Input Voltage (for Vo = 5 to 18V)(for Vo = 20, 24V)

3540

VV

Io Output Current Internally limited

Pt o t Power Dissipation Internally limited

To p Operating Junction Temperature (for L7800 )(for L7800C )

– 55 to + 1500 to + 150

°C°C

T s tg Storage Temperature – 65 to + 150 °C

CONNECTION DIAGRAM AND ORDERING NUMBERS (top view)

THERMAL DATA

Symbol Parameter TO-220 ISOWATT220 TO-3 Unit

Rthj-case

Rthj-amb

Thermal Resistance Junction-case MaxThermal Resistance Junction-ambient Max

350

460

435

oC/WoC/W

Type TO-220 ISOWATT220 TO-3 Output Voltage

L7805L7805CL7852CL7806L7806CL7808L7808CL7885CL7809CL7812L7812CL7815L7815CL7818L7818CL7820L7820CL7824L7824C

L7805CVL7852CV

L7806CV

L7808CVL7885CVL7809CV

L7812CV

L7815CV

L7818CV

L7820CV

L7824CV

L7805CPL7852CP

L7806CP

L7808CPL7885CPL7809CP

L7812CP

L7815CP

L7818CP

L7820CP

L7824CP

L7805TL7805CTL7852CTL7806TL7806CTL7808TL7808CTL7885CTL7809CTL7812TL7812CTL7815TL7815CTL7818TL7818CTL7820TL7820CTL7824TL7824CT

5V5V

5.2V6V6V8V8V

8.5V9V

12V12V15V15V18V18V20V20V24V24V

TO-220 & ISOWATT220 TO-3

L7800 SERIES

2/24

APPLICATION CIRCUIT

SCHEMATIC DIAGRAM

L7800 SERIES

3/24

TEST CIRCUITS

Figure 1 : DC Parameters. Figure 2 : Load Regulation.

Figure 3 : Ripple Rejection.

L7800 SERIES

4/24

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be takeninto account separately. Pulce testing with low duty cycle is used.

ELECTRICAL CHARACTERISTICS FOR L7806 (refer to the test circuits, Tj = -55 to 150 oC,Vi = 15V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vo Output Voltage Tj = 25 oC 5.75 6 6.25 V

Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 9 to 21 V

5.65 6 6.35 V

∆Vo* Line Regulation Vi = 8 to 25 V Tj = 25 oCVi = 9 to 13 V Tj = 25 oC

6030

mVmV

∆Vo* Load Regulation Io = 5 to 1500 mA Tj = 25 oCIo = 250 to 750 mA Tj = 25 oC

10030

mVmV

Id Quiescent Current Tj = 25 oC 6 mA

∆Id Quiescent Current Change Io = 5 to 1000 mA 0.5 mA

∆Id Quiescent Current Change Vi = 9 to 25 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 0.7 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 40 µV/VO

SVR Supply Voltage Rejection Vi = 9 to 19 V f = 120 Hz 65 dB

Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 2.5 V

Ro Output Resistance f = 1 KHz 19 mΩ

Isc Short Circuit Current Vi = 35 V Tj = 25 oC 0.75 1.2 A

Iscp Short Circuit Peak Current Tj = 25 oC 1.3 2.2 3.3 A





4.65 5 5.35 V


31

5025

mVmV


10025

mVmV




∆Vo








L7800 SERIES

5/24





Vo Output Voltage Io = 5 mA to 1 A Po ≤ 15 WVi = 15.5 to 27 V

11.4 12 12.6 V

∆Vo* Line Regulation Vi = 14.5 to 30 V Tj = 25 oCVi = 16 to 22 V Tj = 25 oC

12060

mVmV


10060

mVmV




∆Vo












7.6 8 8.4 V


8040

mVmV


10040

mVmV



∆Id Quiescent Current Change Vi = 11.5 to 25 V 0.8 mA

∆Vo

∆TOutput Voltage Drift Io = 5 mA 1 mV/oC


SVR Supply Voltage Rejection Vi = 11.5 to 21.5 V f = 120 Hz 62 dB





L7800 SERIES

6/24






17.1 18 18.9 V


18090

mVmV


18090

mVmV




∆Vo












14.25 15 15.75 V


15075

mVmV


15075

mVmV



∆Id Quiescent Current Change Vi = 18.5 to 30 V 0.8 mA

∆Vo








L7800 SERIES

7/24




Vo Output Voltage Tj = 25 oC 23 24 25 V


22.8 24 25.2 V


240120

mVmV


240120

mVmV




∆Vo

∆TOutput Voltage Drift Io = 5 mA 3 mV/oC











19 20 21 V


200100

mVmV


200100

mVmV




∆Vo








L7800 SERIES

8/24


ELECTRICAL CHARACTERISTICS FOR L7852C (refer to the test circuits, Tj = 0 to 125 oC,Vi = 10V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)


Vo Output Voltage Tj = 25 oC 5.0 5.2 5.4 V


4.95 5.2 5.45 V


31

10552

mVmV


10552

mVmV




∆Vo

∆TOutput Voltage Drift Io = 5 mA -1.0 mV/oC

eN Output Noise Voltage B = 10Hz to 100KHz Tj = 25 oC 42 µV


Vd Dropout Voltage Io = 1 A Tj = 25 oC 2 V


Isc Short Circuit Current Vi = 35 V Tj = 25 oC 750 mA

Iscp Short Circuit Peak Current Tj = 25 oC 2.2 A





4.75 5 5.25 V


31

10050

mVmV


10050

mVmV




∆Vo








L7800 SERIES

9/24






7.6 8 8.4 V


16080

mVmV


16080

mVmV



∆Id Quiescent Current Change Vi = 10.5 to 25 V 1 mA

∆Vo












5.7 6 6.3 V


12060

mVmV


12060

mVmV




∆Vo








L7800 SERIES

10/24





8.55 9 9.45 V


18090

mVmV


18090

mVmV




∆Vo









ELECTRICAL CHARACTERISTICS FOR L7885C (refer to the test circuits, Tj = 0 to 125 oC,Vi = 14.5V, Io = 500 mA, Ci = 0.33 µF, Co = 0.1 µF unless otherwise specified)


Vo Output Voltage Tj = 25 oC 8.2 8.5 8.8 V


8.1 8.5 8.9 V

∆Vo* Line Regulation Vi = 11 to 27 V Tj = 25 oCVi = 11.5 to 17.5 V Tj = 25 oC

16080

mVmV


16080

mVmV



∆Id Quiescent Current Change Vi = 11 to 27 V 1 mA

∆Vo








L7800 SERIES

11/24






14.25 15 15.75 V


300150

mVmV


300150

mVmV




∆Vo

∆TOutput Voltage Drift Io = 5 mA -1 mV/oC











11.4 12 12.6 V


240120

mVmV


240120

mVmV




∆Vo








L7800 SERIES

12/24






19 20 21 V


400200

mVmV


400200

mVmV




∆Vo












17.1 18 18.9 V


360180

mVmV


360180

mVmV




∆Vo








L7800 SERIES

13/24




Vo Output Voltage Tj = 25 oC 23 24 25 V


22.8 24 25.2 V


480240

mVmV


480240

mVmV




∆Vo








L7800 SERIES

14/24

Figure 6 : Supply Voltage Rejection vs. Frequen-cy.

Figure 7 : Output Voltage vs. Junction Tempera-ture.

Figure 8 : Output Impedance vs. Frequency. Figure 9 : Quiescent Current vs. Junction Tempe-rature.

Figure 4 : Dropout Voltage vs. Junction Tempera-ture.

Figure 5 : Peak Output Current vs. Input/outputDifferential Voltage.

L7800 SERIES

15/24

Figure 12 : Quiescent Current vs. Input Voltage.

Figure 13 : Fixed Output Regulator. Figure 14 : Current Regulator.

Figure 10 : Load Transient Response. Figure 11 : Line Transient Response.

Notes : 1. To specify an output voltage, substitute voltagevalue for ”XX”.

2. Although no output capacitor is needed for sta-bili ty, it does improve transient response.

3. Required if regulator is located an appreciabledis-tance from power supply filter.

VXXIO = + Id

R1

L7800 SERIES

16/24

Figure 15 : Circuit for Increasing Output Voltage. Figure 16 : Adjustable Output Regulator(7 to 30V).

Figure 17 : 0.5 to 10V Regulator. Figure 18 : High Current Voltage Regulator.

IR1 ≥ 5 IdR2

VO = VXX (1 + ) + Id R2R1

VBEQ1R1 =IQ1IREQ –βQ1

VBEQ1IO = IREG + Q1 [IREG – ]R1

R4VO = VXX

R1

L7800 SERIES

17/24

Figure 19 : High Output Current with Short CircuitProtection.

Figure 20 : Tracking Voltage Regulator.

Figure 21 : Split Power Supply (± 15V – 1A). Figure 22 : Negative Output Voltage Circuit.

VBEQ2RSC =ISC

* Against potential latch-up problems.

Figure 23 : Switching Regulator. Figure 24 : High Input Voltage Circuit.

VIN = Vi – (VZ + VBE)

L7800 SERIES

18/24

Figure 27 : High Input and Output Voltage. Figure 28 : Reducing Power Dissipation withDropping Resistor.

Figure 29 : Remote Shutdown.

VO = VXX + VZ1

Vi(min) – VXX – VDROP(max)R =

IO(max) + Id(max)

Figure 25 : High Input Voltage Circuit. Figure 26 : High Output Voltage Regulator.

L7800 SERIES

19/24

Figure 30 : Power AM Modulator (unity voltagegain, Io ≤ 1A).

Figure 31 : Adjustable Output Voltage with Tem-perature Compensation.

Note : The circuit performs well up to 100KHz. Note : Q2 is connected as a diode in order to compensatethe variation of the Q1 VBE with the temperature. C allows aslow rise-time of the VO

Figure 32 : Light Controllers (Vo min = Vxx + VBE).

VO falls when the light goes up VO rises when the light goes up

Figure 33 : Protection against Input Short-circuitwith High Capacitance Loads.

Applications with high capacitance loads and an output volt-age greater than 6 volts need an external diode (see fig. 33)to protect the device against input short circuit. In this casethe input voltage falls rapidly while the output voltage de-creases showly. The capacitance discharges by means ofthe Base-Emitter junction of the series pass transistor in theregulator. If the energy is sufficiently high, the tran-sistor

R2VO = VXX (1 + ) + VBE

R1

L7800 SERIES

20/24

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 11.00 13.10 0.433 0.516

B 0.97 1.15 0.038 0.045

C 1.50 1.65 0.059 0.065

D 8.32 8.92 0.327 0.351

E 19.00 20.00 0.748 0.787

G 10.70 11.10 0.421 0.437

N 16.50 17.20 0.649 0.677

P 25.00 26.00 0.984 1.023

R 4.00 4.09 0.157 0.161

U 38.50 39.30 1.515 1.547

V 30.00 30.30 1.187 1.193

C

D

N

BVU

R

AP

EG

O

P003F

TO-3 MECHANICAL DATA

L7800 SERIES

21/24

DIM.mm inch


A 4.40 4.60 0.173 0.181

C 1.23 1.32 0.048 0.051

D 2.40 2.72 0.094 0.107

D1 1.27 0.050

E 0.49 0.70 0.019 0.027

F 0.61 0.88 0.024 0.034

F1 1.14 1.70 0.044 0.067

F2 1.14 1.70 0.044 0.067

G 4.95 5.15 0.194 0.203

G1 2.4 2.7 0.094 0.106

H2 10.0 10.40 0.393 0.409

L2 16.4 0.645

L4 13.0 14.0 0.511 0.551

L5 2.65 2.95 0.104 0.116

L6 15.2 15.9 0.598 0.625

L7 6.2 6.6 0.244 0.260

L9 3.5 4.2 0.137 0.165

DIA. 3.75 3.85 0.147 0.151

L6

A

C D

E

D1

F

G

L7

L2

Dia.

F1

L5

L4

H2

L9

F2

G1

TO-220 MECHANICAL DATA

P011C

L7800 SERIES

22/24

DIM.mm inch


A 4.4 4.6 0.173 0.181

B 2.5 2.7 0.098 0.106

D 2.5 2.75 0.098 0.108

E 0.4 0.7 0.015 0.027

F 0.75 1 0.030 0.039

F1 1.15 1.7 0.045 0.067

F2 1.15 1.7 0.045 0.067

G 4.95 5.2 0.195 0.204

G1 2.4 2.7 0.094 0.106

H 10 10.4 0.393 0.409

L2 16 0.630

L3 28.6 30.6 1.126 1.204

L4 9.8 10.6 0.385 0.417

L6 15.9 16.4 0.626 0.645

L7 9 9.3 0.354 3.66

Ø 3 3.2 0.118 0.126

L2

A

B

D

E

H G

L6

Ø F

L3

G1

1 2 3

F2

F1

L7

L4

ISOWATT220 MECHANICAL DATA

P011G

L7800 SERIES

23/24

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. Nolicense is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentionedin this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.SGS-THOMSON Microelectronicsproducts are not authorized foruse ascritical components in life support devices or systems without expresswritten approval of SGS-THOMSON Microelectonics.

1994 SGS-THOMSON Microelectronics - All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A

L7800 SERIES

24/24


1N4001

lxv

1N4001 thru 1N4007 Vishay Semiconductorsformerly General Semiconductor

Document Number 88503 www.vishay.com13-Jan-03 1

General Purpose Plastic RectifierReverse Voltage

50 to 1000VForward Current 1.0A

Maximum Ratings & Thermal Characteristics Ratings at 25°C ambient temperature unless otherwise specified.

Parameter Symb. 1N 1N 1N 1N 1N 1N 1N Unit4001 4002 4003 4004 4005 4006 4007

Maximum repetitive peak reverse voltage VRRM 50 100 200 400 600 800 1000 V

* Maximum RMS voltage VRMS 35 70 140 280 420 560 700 V

* Maximum DC blocking voltage VDC 50 100 200 400 600 800 1000 V

* Maximum average forward rectified current0.375" (9.5mm) lead length at TA = 75°C IF(AV) 1.0 A

* Peak forward surge current 8.3ms single half sine-wave IFSM 30 Asuperimposed on rated load (JEDEC Method) TA = 75°C

* Maximum full load reverse current, full cycle average 0.375" (9.5mm) lead length TL = 75°C IR(AV) 30 µA

Typical thermal resistance(1) RθJA 50 °C/WRθJL 25

* Maximum DC blocking voltage temperature TA +150 V

* Operating junction and storage temperature range TJ, TSTG –50 to +175 °C

Electrical Characteristics Ratings at 25°C ambient temperature unless otherwise specified.

Maximum instantaneous forward voltage at 1.0A VF 1.1 V

* Maximum DC reverse current TA = 25°C 5.0at rated DC blocking voltage TA = 125°C IR 50 µA

Typical junction capacitance at 4.0V, 1MHz CJ 15 pF

Note: (1) Thermal resistance from junction to ambient at 0.375” (9.5mm) lead length, P.C.B. mounted *JEDEC registered values

DO-204AL(DO-41) Features

• Plastic package has Underwriters Laboratories Flammability Classification 94V-0

• Construction utilizes void-free molded plastic technique• Low reverse leakage• High forward surge capability• High temperature soldering guaranteed: 350°C/10 seconds,

0.375" (9.5mm) lead length, 5 lbs. (2.3kg) tension

Mechanical DataCase: JEDEC DO-204AL, molded plastic bodyTerminals: Plated axial leads, solderable per MIL-STD-750, Method 2026Polarity: Color band denotes cathode endMounting Position: AnyWeight: 0.012 oz., 0.3 g

0.107 (2.7)0.080 (2.0)

0.034 (0.86)0.028 (0.71)

DIA.

1.0 (25.4) MIN.

1.0 (25.4) MIN.

0.205 (5.2)0.160 (4.1)

DIA.

NOTE: Lead diameter is for suffix "E" part numbers0.026 (0.66)0.023 (0.58)

Dimensions in inches and (millimeters)

1N4001 thru 1N4007Vishay Semiconductorsformerly General Semiconductor

www.vishay.com Document Number 885032 13-Jan-03

Ratings and Characteristic Curves (TA = 25°C unless otherwise noted)

00

Fig. 1 – Forward Current Derating Curve

Ave

rage

For

war

d R

ectif

ied

Cur

rent

(A

)

Ambient Temperature (°C)

0

Fig. 4 – Typical Reverse Characteristics

5.0

Fig. 2 – Maximum Non-Repetitive Peak Forward Surge Current

Fig. 5 – Typical Junction Capacitance

Fig. 3 – Typical Instantaneous Forward Characteristics

Fig. 6 – Typical Transient Thermal Impedance

25 50 75 100 125 150 175

0.2

0.4

0.6

0.8

1.060HZ Resistive or

Inductive Load

0.375" (9.5mm) Lead Length

0.2 x 0.2" (5.0 x 5.0mm) Copper Pads

1 10 100

Number of Cycles at 60HZ

10

15

20

25

30

Pea

k F

orw

ard

Sur

ge C

urre

nt (

A)

TA = 75°C8.3ms Single Half Sine-Wave (JEDEC Method)

0.6 0.8 1.0 1.2 1.4 1.6 1.8

Instantaneous Forward Voltage (V)

0.01

0.1

1

10

20

Inst

anta

neou

s F

orw

ard

Cur

rent

(A

)

0.01

0.1

1

10

100

1,000

Inst

anta

neou

s R

ever

se C

urre

nt (

µA)

60 80 10020 40

Percentage of Peak Reverse Voltage (%)

TJ = 25°C

TJ = 150°C

TJ = 100°C

0.1 1 10 100

Reverse Voltage (V)

1

10

100

Junc

tion

Cap

acita

nce

(pF

)

TJ = 25°Cf = 1.0MHZ

Vsig = 50mVp-p

0.01 0.1 1 10 100

t -- Pulse Duration (sec)

0.1

10

100

1

Tran

sien

t The

rmal

Impe

danc

e (°

C/W

)

TJ = 25°C Pulse Width = 300µs 1% Duty Cycle


GL494

lxviii

GL494

1

GL494 PWM CONTROL CIRCUIT

Description The GL494 incorporates on a single monolithic chip all the

functions required in the construction of a pulse-width-

modulation control circuit. Designed primarily for power

supply control, the GL494 contains an on-chip 5-volt

regulator, two error amplifiers, adjustable oscillator, dead-

time control comparator, pulse-steering flip-flop, and

output-control circuitry. The uncommitted output

transistors pro-vide either common-emitter or emitter-

follower output capability. Push-pull or single-ended

output operation may be selected through the output-

control function. The ar-chitecture of the GL494 prohibits

the possibility of either output being pulsed twice during

push-pull operation.

Features Complete PWM Power Control Circuitry Uncommitted Outputs for 200mA Sink or Source Output Control Selects Single-Ended or Push-Pull

Operation Internal Circuitry Prohibits Double Pulse at Either

Output Internal Regulator Provides a Stable 5V Reference

Supply Variable Dead-Time Provides Control Over Total

Range

Pin Configuration Function Table

Output Control Output Function

Grounded Single-ended or Parallel Output

At refV Normal Push-Pull Operation

Block Diagram

OSCILLATOR

REFERENCE

REGULATOR

NONINV INPUT

INV. INPUT

FEEDBACK

DEAD TIME CONTROL

Cr

Rr

GND

C1

NON INV INPUT

INV. INPUT

REF. OUT

OUTPUT CONTROL

Vcc

C2

E2

E1

RT

CT

DEAD TIME

CONTROL

NONINVERTING(1) INPUT

INVERTING (2) INPUT

NONINVERTING(16) INPUT

INVERTING (15) INPUT

FEEDBACK

ERROR AMPLIFIERS PWM

COMPARATOR

OUTPUT CONTROL

(See Function Table) PULSE STEERING

FLIP FLOP

VCC

REF OUT

GND

E1(9) C1(8)

E1(10) C2(11)

(4)

(3) (7)

(12)

(14)

(13)

T

Q

Q

0.1V

+

+

−

−

ERROR AMP1

ERROR AMP2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GL494

2

Absolute Maximum Ratings Supply Voltage, CCV ……………………………………………………………………….. 41 V Amplifier Input Voltage ……………………………………………………………….. CCV +0.3 V Collector Output Voltage ……………………………………………………………………… 41 V Continuous Total dissipation at (or below) 25 C° ………………………………………. 1000 mW Operating Free-Air Temperature Range ……………………………………………… -20 to 85 C° Storage Temperature Range ……………………………………………………….….. -65 to 150 C° Collector Output Current ………………………………………………………………….. 250 mA

Recommended Operation Conditions

PARAMETER MIN MAX UNIT

Supply Voltage, CCV 7 40 V

Amplifier Input Voltage, 1V -0.3 CCV -2 V

Collector Output Voltage, Vo 40 V

Collector Output Current (Each Transistor)

200 mA

Current Into Feed back Terminal 0.3 mA

Timing Capacitor, TC 0.47 10,000 nF

Timing Resistor, TR 1.8 500 ΩK

Oscillator Frequency 1 300 KHz

Operating Free-Air Temperature -20 85 C° Electrical Characteristics (Temperature C85~20 °− , CCV =15V, f=10KHz) Reference Section

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Output voltage ( refV ) mA1IO = 4.75 5 5.25 V

Input regulation V7VCC = to 40V, C25TA °= 2 25 mV

Output regulation 1IO = to 10mA, C25TA °= 1 15 mV

Output Voltage change with temperature C20TA °−= to C85° 0.2 1 %

Short-circuit Output current(2)

0Vref = 35 mA

Oscillator Section


Frequency F01.0CT µ= , Ω= k12RT 10 KHz

Standard deviation of frequency (3)

All values of CCV , ATT T,R,C Constant

10 %

Frequency change with Voltage

V7VCC = to 40V, C25TA °= 0.1 %

Frequency change with temperature

F01.0CT µ= , Ω= k12RT C20TA °−= to C85° 2 %

GL494

3

Dead Time Control Section


Input bias current (pin 4) VI=0 to 5.25V -2 -10 Aµ

Maximum duty cycle, Each output )4pin(IV =0V 45 %

Zero duty cycle 3 3.3 V Input threshold voltage (pin 4) Maximum duty cycle 0 V

Error Amp Sections


Input offset voltage V5.2V )3PIN(O = 2 10 mV

Input offset current V5.2V )3PIN(O = 25 250 nA

Input bias current V5.2V )3PIN(O = 0.2 1 Aµ

LOW -0.3 Common-mode input voltage range

V7VCC = to 40V HIGH 2VCC −

V

Open-loop voltage Amplification

5.0V,V3V OO ==∆ to3.5V

70 95 dB

Unity-gain bandwidth 800 KHz

Common-mode rejection ratio V40VCC = , C25TA °= 65 80 dB

Output sink current (pin 3) mV15VID −= to –5V,

V7.0V )3pin(O = 0.3 0.7 mA

Output source current (pin 3) mV15VID = to 5V,

V5.3V )3pin(O = -2 mA

PWM Comparaor Section


Input threshold voltage (pin 3) Zero duty cycle 4 4.5 V

Input sink current (pin 3) V7.0V )3pin(O = 0.3 0.7 mA

Switching Characteristics


Output Voltage rise time 100 200 ns

Output Voltage fall time

Common-emitter configuration, See Test Circuit 3 25 100 ns

Output Voltage rise time 100 200 ns

Output Voltage fall time

Emitter-follower configuration, See Test Circuit 4 40 100 ns

GL494

4

Output Section


Collector off-state current V40V,V40V CCCE == 2 100 mA

Emitter off-state current 0V,V40VV ECCC === -100 mA

Common-emitter mA200I,0V CE == 1.1 1.3 Collector-emitter Saturation voltage Emitter-follower mA200I,V15V EC −== 1.5 2.5

V

Output control input current refI VV = 3.5 mA

Total Device


V15VCC = 6 10 mA Standby supply current

All other inputs & Outputs open V40VCC = 9 15 mA

Average supply current V2V )4pin( =

See Test circuit 1 7.5 mA

Notes:

(1) All typical values except for temperature coefficients are at C25TA °=

(2) Duration of the short circuit should not exceed one second.

(3) Standard deviation is a measure of the statistical distribution about the mean as derived from the formula

1N

)XX(N

1n

2n

−

−

=σ∑

=

GL494

5

Parameter Measurement Information

1.Dead time and Feedback Control 2. Error Amplifier Characteristics 3. Common-Emitter Configuration

TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM

DEAD TIME (4) (8) C1 FEEDBACK (3) (9) E1 Re (6) Cr (5) (11) C2 (+) (16) ERROR (12) E2 (-) (15) AMP (+) (1) ERROR (-) (2) AMP OUTPUT CONTROL

Vcc=15V

TEST INPUTS

OUTPUT 1

OUTPUT 2

(14) REF OUT GND (7)

(13)

50kΩ

150Ω 2W

150Ω 2W

12kΩ

0.01µF

VOLTAGE AT C1

VOLTAGE AT C2

VOLTAGE AT CT

DEAD-TIME

CONTROL INTPUT

FEEDBACK

MAX DUTY CYCLE

MAX

THRESHOLD VOLTAGE

THRESHOLD VOLTAGE

Vcc

Vcc 0

0

0% 0%

0V

0.7V

V1

ERROR AMPLIFIER UNDER TEST

FEEDBACK TERMINAL

OTHER ERROR AMPLIFIER

VREF

–

–

+

+

(EACH OUTPUT CIRCUIT)

OUTPUT

15V

68Ω 2W

CL=15pF (INCLUDES PROBE AND JIG CAPACITANCE)

90% 90%

10% 10%

tf tr

TEST CIRCUIT VOLTAGE WAVEFORMS

GL494

6

4. Emitter-Follower Configuration

TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM

Typical Performance Curves

(EACH OUTPUT EIRCUIT)

15V

68Ω 2W

OUTPUT

CL=15pF(INCLUDES PROBE AND

JIG CAPACITANCE)

90% 90%

10% 10%

tf tr

300k

100k

10k

1k

100

30

100

90

80

70

60

50

40

30

20

10

0 1k 2k 5k 10k 20k 50k 100k 200k 500k 1M 1.0 10 100 1k 10k 100k 1M

20

0

-20

-40

-60

-80

-100

-120

-140

-160

-80

AV

OL,

OP

EN

-LO

OP

VO

AT

AG

E G

AIN

(db

)

10

9

8

7

6

5

4

3

2

1

0

50

40

30

20

10

0 100 1k 10k 100k 0 1.0 2.0 3.0 3.5

%D

T. P

ER

CE

NT

DE

AD

TIM

E, E

AC

H O

UT

PU

T

AC

H O

UT

PU

T

FIGURE 1 – OSCILLATOR FREQUENCY versus TIMING RESISTANCE

FIGURE 2 – OPEN LOOP VOLTAGE GAIN AND PHASE versus FREQUENCY

FIGURE 3 – PERCENT DEAD TIME versus OSCILLATOR FREQUENCY

FIGURE 4 – PERCENT DUTY CYCLE versus DEAD-TIME CONTROL VOLTAGE

RT, TIMING RESISTANCE (Ω) f, FREQUENCY (Hz)

fo, OSCILLATOR FREQUENCY (Hz) DEAD TIME CONTROL VOLTAGE (V)

Vcc=15V 0.001 µF

CT=0.01 µF

0.1 µF

0.1 µF

AVOL

0.01 µF

CT=0.01 µF

Vcc=15V Vo=3V RL=2kΩ

Vcc=15V Voc=Vref V(PIN4)=0V

Vcc=15V Voc=Vref 1) CT=0.01

RT=10k 2) CT=0.001

RT=30K

1

2

θ

GL494

7

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0

0 50 100 150 200 250 0 50 100 150 200 250

0 5.0 10 15 20 25 30 35 40

VC

E(S

AT

), S

AT

UR

AT

ION

VO

LTA

GE

(V

)

IE, EMITTER CURRENT (mA)

FIGURE 5 – EMITTER-FOLLOWER CONFIGURATION OUTPUT-SATURATION VOLTAGE versus EMITTER CURRENT

VC

E(S

AT

), S

AT

UR

AT

ION

VO

LTA

GE

(V

)

Icc,

SU

PP

LY C

UR

RE

NT

(m

A)

Ic, COLLECTOR CURRENT (mA)

Vcc, SUPPLY VOLTAGE (V)

FIGURE 6 – COMMON-EMITTER CONFIGURATION OUTPUT-SATURATION VOLTAGE versus COLLECTOR CURRENT

FUGURE 7 – STANDBY-SUPPLY CURRENT versus SUPPLY VOLTAGE

Vcc=15V Vcc=15V


L293

lxxvi

L293, L293DQUADRUPLE HALF-H DRIVERS

SLRS008B – SEPTEMBER 1986 – REVISED JUNE 2002

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Featuring Unitrode L293 and L293DProducts Now From Texas Instruments

Wide Supply-Voltage Range: 4.5 V to 36 V

Separate Input-Logic Supply

Internal ESD Protection

Thermal Shutdown

High-Noise-Immunity Inputs

Functional Replacements for SGS L293 andSGS L293D

Output Current 1 A Per Channel(600 mA for L293D)

Peak Output Current 2 A Per Channel(1.2 A for L293D)

Output Clamp Diodes for InductiveTransient Suppression (L293D)

description

The L293 and L293D are quadruple high-currenthalf-H drivers. The L293 is designed to providebidirectional drive currents of up to 1 A at voltagesfrom 4.5 V to 36 V. The L293D is designed toprovide bidirectional drive currents of up to600-mA at voltages from 4.5 V to 36 V. Bothdevices are designed to drive inductive loads suchas relays, solenoids, dc and bipolar steppingmotors, as well as other high-current/high-voltageloads in positive-supply applications.

All inputs are TTL compatible. Each output is a complete totem-pole drive circuit, with a Darlington transistorsink and a pseudo-Darlington source. Drivers are enabled in pairs, with drivers 1 and 2 enabled by 1,2EN anddrivers 3 and 4 enabled by 3,4EN. When an enable input is high, the associated drivers are enabled and theiroutputs are active and in phase with their inputs. When the enable input is low, those drivers are disabled andtheir outputs are off and in the high-impedance state. With the proper data inputs, each pair of drivers formsa full-H (or bridge) reversible drive suitable for solenoid or motor applications.

On the L293, external high-speed output clamp diodes should be used for inductive transient suppression.

A VCC1 terminal, separate from VCC2, is provided for the logic inputs to minimize device power dissipation.

The L293and L293D are characterized for operation from 0°C to 70°C.

Copyright 2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

HEAT SINK ANDGROUND

HEAT SINK ANDGROUND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1,2EN1A1Y

2Y2A

VCC2

VCC14A4Y

3Y3A3,4EN

N, NE PACKAGE(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1,2EN1A1YNCNCNC

NCNC2Y2A

VCC2

VCC14A4YNCNCNC

NCNC3Y3A3,4EN

DWP PACKAGE(TOP VIEW)

HEAT SINK ANDGROUND

HEAT SINK ANDGROUND



2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

block diagram

10

3

4

5

6

7

8 9

10

11

12

13

14

15

161

210

1

10

2

4

3

M

M

M

10

10

10

VC

VCC1

NOTE: Output diodes are internal in L293D.

TEXAS INSTRUMENTSAVAILABLE OPTIONS

PACKAGE

TAPLASTIC

DIP(NE)

0°C to 70°CL293NEL293DNE

AVAILABLE OPTIONS

PACKAGED DEVICES

TASMALL

OUTLINE(DWP)

PLASTICDIP(N)

0°C to 70°CL293DWPL293DDWP

L293NL293DN

The DWP package is available taped and reeled. Addthe suffix TR to device type (e.g., L293DWPTR).




FUNCTION TABLE(each driver)

INPUTS† OUTPUTA EN Y

H H H

L H L

X L Z

H = high level, L = low level, X = irrelevant,Z = high impedance (off)† In the thermal shutdown mode, the output is

in the high-impedance state, regardless ofthe input levels.

logic diagram

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

2

1

7

10

9

15

3

6

11

14

1A

1,2EN

2A

3A

3,4EN

4A

1Y

2Y

3Y

4Y

schematics of inputs and outputs (L293)

Input

VCC2

Output

GND

TYPICAL OF ALL OUTPUTSEQUIVALENT OF EACH INPUT

VCC1

CurrentSource

GND




schematics of inputs and outputs (L293D)

Input

VCC2

Output

GND

TYPICAL OF ALL OUTPUTSEQUIVALENT OF EACH INPUT

VCC1

CurrentSource

GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, VCC1 (see Note 1) 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output supply voltage, VCC2 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range, VO –3 V to VCC2 + 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak output current, IO (nonrepetitive, t ≤ 5 ms): L293 ±2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak output current, IO (nonrepetitive, t ≤ 100 µs): L293D ±1.2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current, IO: L293 ±1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current, IO: L293D ±600 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total dissipation at (or below) 25°C free-air temperature (see Notes 2 and 3) 2075 mW. . . . . . . Continuous total dissipation at 80°C case temperature (see Note 3) 5000 mW. . . . . . . . . . . . . . . . . . . . . . . . . Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to the network ground terminal.2. For operation above 25°C free-air temperature, derate linearly at the rate of 16.6 mW/°C.3. For operation above 25°C case temperature, derate linearly at the rate of 71.4 mW/°C. Due to variations in individual device electrical

characteristics and thermal resistance, the built-in thermal overload protection may be activated at power levels slightly above orbelow the rated dissipation.




recommended operating conditions

MIN MAX UNIT

Supply voltageVCC1 4.5 7

VSupply voltageVCC2 VCC1 36

V

VIH High level input voltageVCC1 ≤ 7 V 2.3 VCC1 V

VIH High-level input voltageVCC1 ≥ 7 V 2.3 7 V

VIL Low-level output voltage –0.3† 1.5 V

TA Operating free-air temperature 0 70 °C† The algebraic convention, in which the least positive (most negative) designated minimum, is used in this data sheet for logic voltage levels.

electrical characteristics, VCC1 = 5 V, VCC2 = 24 V, TA = 25°CPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltageL293: IOH = –1 AL293D: IOH = –0.6 A

VCC2–1.8 VCC2–1.4 V

VOL Low-level output voltageL293: IOL = 1 AL293D: IOL = 0.6 A

1.2 1.8 V

VOKH High-level output clamp voltage L293D: IOK = –0.6 A VCC2 + 1.3 V

VOKL Low-level output clamp voltage L293D: IOK = 0.6 A 1.3 V

IIH High level input currentA

VI = 7 V0.2 100

µAIIH High-level input currentEN

VI = 7 V0.2 10

µA

IIL Low level input currentA

VI = 0–3 –10

µAIIL Low-level input currentEN

VI = 0–2 –100

µA

All outputs at high level 13 22

ICC1 Logic supply current IO = 0 All outputs at low level 35 60 mA

All outputs at high impedance 8 24

All outputs at high level 14 24

ICC2 Output supply current IO = 0 All outputs at low level 2 6 mA

All outputs at high impedance 2 4

switching characteristics, VCC1 = 5 V, VCC2 = 24 V, TA = 25°C

PARAMETER TEST CONDITIONSL293NE, L293DNE

UNITPARAMETER TEST CONDITIONSMIN TYP MAX

UNIT

tPLH Propagation delay time, low-to-high-level output from A input 800 ns

tPHL Propagation delay time, high-to-low-level output from A inputCL = 30 pF See Figure 1

400 ns

tTLH Transition time, low-to-high-level outputCL = 30 pF, See Figure 1

300 ns

tTHL Transition time, high-to-low-level output 300 ns

switching characteristics, VCC1 = 5 V, VCC2 = 24 V, TA = 25°C

PARAMETER TEST CONDITIONS

L293DWP, L293NL293DDWP, L293DN UNIT

MIN TYP MAX

tPLH Propagation delay time, low-to-high-level output from A input 750 ns

tPHL Propagation delay time, high-to-low-level output from A inputCL = 30 pF See Figure 1

200 ns

tTLH Transition time, low-to-high-level outputCL = 30 pF, See Figure 1

100 ns

tTHL Transition time, high-to-low-level output 350 ns




PARAMETER MEASUREMENT INFORMATION

Output

CL = 30 pF(see Note A)

VCC1

Input

3 V

TEST CIRCUIT

tf tr3 V

0

tPHL

VOH

tTHL tTLH

VOLTAGE WAVEFORMS

tPLH

Output

Input

VOL

tw

NOTES: A. CL includes probe and jig capacitance.B. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 10 µs, PRR = 5 kHz, ZO = 50 Ω.

PulseGenerator

(see Note B)

5 V 24 V

VCC2

A

EN

Y90% 90%

50%

10%

50%

10%

90% 90%

50%

10%

50%

10%

Figure 1. Test Circuit and Voltage Waveforms




APPLICATION INFORMATION

24 V5 V

10 kΩ

VCC1VCC2

Control A

Control B

4, 5, 12, 13

GND

ThermalShutdown

Motor

16 3

3

6

11

14

4Y

3Y

2Y

1Y

1,2EN

1A

2A

3,4EN

3A

4A

15

10

9

7

2

1

Figure 2. Two-Phase Motor Driver (L293)





24 V5 V

10 kΩ

VCC1 VCC2

16 3

1,2EN1

1A2

2A

7

3,4EN

9

3A10

4A15

Control A

Control B

4, 5, 12, 13

GND

ThermalShutdown

Motor

1Y

3

2Y

6

3Y

11

4Y

14

Figure 3. Two-Phase Motor Driver (L293D)





EN 3A M1 4A M2

H H Fast motor stop H Run

H L Run L Fast motor stop

L XFree-running motorstop

XFree-running motorstop

L = low, H = high, X = don’t care

EN 1A 2A FUNCTION

H L H Turn right

H H L Turn left

H L L Fast motor stop

H H H Fast motor stop

L X X Fast motor stop

L = low, H = high, X = don’t care

VCC2 SES5001

1/2 L293

4, 5, 12, 13

10

SES5001

VCC1

EN

1511 14

16

9

M2

M1

3A 4A

8

Figure 4. DC Motor Controls(connections to ground and to

supply voltage)

GND

2 × SES5001

1/2 L293

4, 5, 12, 13

367

8

1

216

VCC2

2 × SES5001

2A 1A

VCC1

EN

M

Figure 5. Bidirectional DC Motor Control

GND





3

4

5

6

7

8

1

2

9

10

11

12

13

14

15

16

+

+

+

+

D7

D8 D4

D3

L2 IL2

C1

D5 D1

D6 D2

VCC1L293

IL1/IL2 = 300 mA

0.22 µF

VCC2 L1 IL1

D1–D8 = SES5001

Figure 6. Bipolar Stepping-Motor Control

mounting instructions

The Rthj-amp of the L293 can be reduced by soldering the GND pins to a suitable copper area of the printedcircuit board or to an external heatsink.

Figure 9 shows the maximum package power PTOT and the θJA as a function of the side of two equal squarecopper areas having a thickness of 35 µm (see Figure 7). In addition, an external heat sink can be used (seeFigure 8).

During soldering, the pin temperature must not exceed 260°C, and the soldering time must not be longer than12 seconds.

The external heatsink or printed circuit copper area must be connected to electrical ground.





Copper Area 35-µm Thickness

Printed Circuit Board

Figure 7. Example of Printed Circuit Board Copper Area (used as heat sink)

11.9 mm

17.0 mm

38.0 mm

Figure 8. External Heat Sink Mounting Example(θJA = 25°C/W)





3

1

0

2

0 10 20

P

4

MAXIMUM POWER AND JUNCTION vs

THERMAL RESISTANCE

30

TOT

– P

ow

er D

issi

pat

ion

– W

60

20

0

40

80

θ JA

– T

her

mal

Res

ista

nce

–°C

/W

40

Side – mm

Figure 9

θJA

PTOT (TA = 70°C)

50

5

3

1

0

2

–50 0 50

4

MAXIMUM POWER DISSIPATIONvs

AMBIENT TEMPERATURE

100

TA – Ambient Temperature – °C

With Infinite Heat Sink

Free Air

Heat Sink With θJA = 25°C/W

Figure 10

150P

TOT

– P

ow

er D

issi

pat

ion

– W

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third–party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:

Texas InstrumentsPost Office Box 655303Dallas, Texas 75265

Copyright 2002, Texas Instruments Incorporated


MAX1112

cxxxvii

General DescriptionThe MAX1112/MAX1113 are low-power, 8-bit, 8-chan-nel analog-to-digital converters (ADCs) that feature aninternal track/hold, voltage reference, clock, and serialinterface. They operate from a single +4.5V to +5.5Vsupply and consume only 135µA while sampling atrates up to 50ksps. The MAX1112’s 8 analog inputsand the MAX1113’s 4 analog inputs are software-con-figurable, al lowing unipolar/bipolar and single-ended/differential operation.

Successive-approximation conversions are performedusing either the internal clock or an external serial-inter-face clock. The full-scale analog input range is deter-mined by the 4.096V internal reference, or by anexternally applied reference ranging from 1V to VDD.The 4-wire serial interface is compatible with the SPI™,QSPI™, and MICROWIRE™ serial-interface standards.A serial-strobe output provides the end-of-conversionsignal for interrupt-driven processors.

The MAX1112/MAX1113 have a software-program-mable, 2µA automatic power-down mode to minimizepower consumption. Using power-down, the supplycurrent is reduced to 13µA at 1ksps, and only 82µA at10ksps. Power-down can also be controlled using theSHDN input pin. Accessing the serial interface automat-ically powers up the device.

The MAX1112 is available in 20-pin SSOP and DIPpackages. The MAX1113 is available in small 16-pinQSOP and DIP packages.

________________________ApplicationsPortable Data Logging

Hand-Held Measurement Devices

Medical Instruments

System Diagnostics

Solar-Powered Remote Systems

4–20mA-Powered Remote Data-Acquisition Systems

____________________________Features♦ +4.5V to +5.5V Single Supply

♦ Low Power: 135µA at 50ksps13µA at 1ksps

♦ 8-Channel Single-Ended or 4-Channel DifferentialInputs (MAX1112)

♦ 4-Channel Single-Ended or 2-Channel DifferentialInputs (MAX1113)

♦ Internal Track/Hold; 50kHz Sampling Rate

♦ Internal 4.096V Reference

♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs

♦ Total Unadjusted Error: ±1LSB (max)±0.3LSB (typ)

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+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCs

________________________________________________________________ Maxim Integrated Products 1

INPUTSHIFT

REGISTER CONTROLLOGIC

INTCLOCK

OUTPUTSHIFT

REGISTER

+4.096VREFERENCE

T/HANALOGINPUTMUX

8-BITSAR ADC

IN

DOUT

SSTRB

VDD

DGND

AGND

SCLK

DIN

CH0CH1

CH3CH2

CH7*CH6*CH5*CH4*

COM

REFOUT

*MAX1112 ONLY

REFIN

OUTREF

CLOCK

MAX1112MAX1113

CS

SHDN

Functional Diagram

19-1231; Rev 1; 10/98

PART

MAX1112CPP

MAX1112CAP 0°C to +70°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

20 Plastic DIP

20 SSOP

EVALUATION KIT

AVAILABLE

Ordering Information

Ordering Information continued at end of data sheet.

*Dice are specified at TA = +25°C, DC parameters only.

Pin Configurations appear at end of data sheet.

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.

MAX1112C/D 0°C to +70°C Dice*

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.For small orders, phone 1-800-835-8769.

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

VDD to AGND..............................................................-0.3V to 6VAGND to DGND.......................................................-0.3V to 0.3VCH0–CH7, COM, REFIN,

REFOUT to AGND ...................................-0.3V to (VDD + 0.3V)Digital Inputs to DGND ...............................................-0.3V to 6VDigital Outputs to DGND............................-0.3V to (VDD + 0.3V)Continuous Power Dissipation (TA = +70°C)

16 Plastic DIP (derate 10.53mW/°C above +70°C) ......842mW16 QSOP (derate 8.30mW/°C above +70°C)................667mW16 CERDIP (derate 10.00mW/°C above +70°C) ..........800mW

20 Plastic DIP (derate 11.11mW/°C above +70°C) ......889mW20 SSOP (derate 8.00mW/°C above +70°C) ................640mW20 CERDIP (derate 11.11mW/°C above +70°C) ..........889mW

Operating Temperature RangesMAX1112C_P/MAX1113C_E................................0°C to +70°CMAX1112E_P/MAX1113E_E .............................-40°C to +85°CMAX1112MJP/MAX1113MJE..........................-55°C to +125°C

Storage Temperature Range .............................-65°C to +150°CLead Temperature (soldering, 10sec) .............................+300°C

ELECTRICAL CHARACTERISTICS(VDD = +4.5V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversioncycle (50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.)

-3dB rolloff MHz1.5Small-Signal Bandwidth

kHz800

VCH_ = 4.096Vp-p, 25kHz (Note 3)

External reference, 4.096V

No missing codes over temperature

CONDITIONS

Full-Power Bandwidth

±1Internal or external reference LSBGain Error (Note 2)

dB-75Channel-to-Channel Crosstalk

dB68SFDRSpurious-Free Dynamic Range

dB-70THDTotal Harmonic Distortion (up to the 5th harmonic)

LSB±0.1Channel-to-Channel Offset Matching

ppm/°C±0.8Gain Temperature Coefficient

LSB±1DNLDifferential Nonlinearity

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX111_C/E LSB±0.3 ±1TUETotal Unadjusted Error

Bits8Resolution

dB49SINADSignal-to-Noise and Distortion Ratio

LSB±0.1 ±0.5INLRelative Accuracy (Note 1)

LSB±0.3 ±1Offset Error

DC ACCURACY

DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock)

µA

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ELECTRICAL CHARACTERISTICS (continued)(VDD = +4.5V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversioncycle (50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.)

On/off leakage current, VCH_ = 0V or VDD

Used for data transfer only

(Note 5)

External clock, 2MHz

CONDITIONS

ppm/°C±50

mA6REFOUT Short-Circuit Current

pF18Input Capacitance

µA±0.01 ±1Multiplexer Leakage Current

1

2

50 500

kHz400Internal Clock Frequency

0mA to 0.5mA output load mV4.5Load Regulation (Note 7)

ns10Aperture Delay

µs1tACQTrack/Hold Acquisition Time


ps

V1 VDD + 50mV

Input Voltage Range

(Note 8) µA1 20Input Current

<50Aperture Jitter

External clock, 500kHz, 10 clocks/conversion 20

Internal clockµs

25 55tCONVConversion Time (Note 4)

Bipolar input, COM = VREFIN / 2

Unipolar input, COM = 0V

COM ±VREFIN / 2

V

0 VREFINInput Voltage Range, Single-Ended and Differential (Note 6)

V3.936 4.096 4.256REFOUT Voltage

External Clock-Frequency RangeMHz

kHz

Capacitive Bypass at REFOUT µF

REFOUT Temperature Coefficient

V4.5 5.5VDDSupply Voltage

VDD = 4.5V to 5.5V; external reference,4.096V; full-scale input

mV±0.4 ±4PSRPower-Supply Rejection (Note 9)

2Power-down

3.2 10

Software

SHDN at DGND

Operating mode 135 250Full-scale inputCLOAD = 10pF Reference disabled 95

IDD µASupply Current

CONVERSION RATE

ANALOG INPUT

INTERNAL REFERENCE

EXTERNAL REFERENCE AT REFIN

POWER REQUIREMENTS

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4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)(VDD = +4.5V to +5.5V; unipolar input mode; COM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversioncycle (50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.)

CS = VDD (Note 5)

CS = VDD

ISOURCE = 0.5mA

ISINK = 5mA

SHDN = open

SHDN = 0V or VDD

(Note 5)

Digital inputs = 0V or VDD

SHDN = open

CONDITIONS

pF15COUTThree-State Output Capacitance

µA±0.01 ±10ILThree-State Leakage Current

VVDD - 0.5VOHOutput High Voltage

V0.4

VOLOutput Low Voltage

nA±100SHDN Maximum Allowed Leakagefor Mid-Input

VVDD / 2VFLTSHDN Voltage, Floating

µA±4SHDN Input Current

VVDD - 0.4VSHSHDN Input High Voltage

V0.8VILDIN, SCLK, CS Input Low Voltage

V1.1 VDD - 1.1

ISINK = 16mA

VSM

0.8

pF15CINDIN, SCLK, CS Input Capacitance

µA±1IINDIN, SCLK, CS Input Leakage

SHDN Input Mid-Voltage

V0.2VHYSTDIN, SCLK, CS Input Hysteresis


V0.4VSLSHDN Input Low Voltage

VVIHDIN, SCLK, CS Input High Voltage 3

DIGITAL INPUTS: DIN, SCLK, CS

DIGITAL OUTPUTS: DOUT, SSTRB

SHDN INPUT

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ns100tCSS

Figure 1, external clock mode only, CLOAD = 100pF

ns

CS to SCLK Rise Setup

240

Figure 1, CLOAD = 100pF ns

20 200

ns0tCSH

CONDITIONS

CS to SCLK Rise Hold

240tDVCS Fall to Output Enable

Figure 2, CLOAD = 100pF ns240tTRCS Rise to Output Disable

tSDVCS Fall to SSTRB Output Enable(Note 5)

Figure 2, external clock mode only, CLOAD = 100pF

ns240tSTRCS Rise to SSTRB Output Disable (Note 5)

Figure 11, internal clock mode only ns0tSCKSSTRB Rise to SCLK Rise (Note 5)

ns200tCHSCLK Pulse Width High

ns200tCLSCLK Pulse Width Low

CLOAD = 100pF ns240tSSTRBSCLK Fall to SSTRB

ns0tDHDIN to SCLK Hold

µs1tACQTrack/Hold Acquisition Time

ns100tDSDIN to SCLK Setup


TIMING CHARACTERISTICS (Figures 8 and 9)(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)

Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.Note 2: VREFIN = 4.096V, offset nulled.Note 3: On-channel grounded; sine wave applied to all off-channels.Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.Note 5: Guaranteed by design. Not subject to production testing.Note 6: Common-mode range for the analog inputs is from AGND to VDD.Note 7: External load should not change during the conversion for specified accuracy.Note 8: External reference at 4.096V, full-scale input, 500kHz external clock.Note 9: Measured as | VFS (4.5V) - VFS (5.5V) |.Note 10: 1µF at REFOUT; internal reference settling to 0.5LSB.

ns20 240

tDOSCLK Fall to Output Data ValidFigure 1,CLOAD = 100pF

MAX111_C/E

MAX111_M

External reference 20

Internal reference (Note 10)

µs

24tWAKEWakeup Time

ms

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6 _______________________________________________________________________________________

__________________________________________Typical Operating Characteristics(VDD = +5.0V; fSCLK = 500kHz; external clock (50% duty cycle); RL = ∞; TA = +25°C, unless otherwise noted.)

180

100-60 140

SUPPLY CURRENT vs. TEMPERATURE

120

MAX

1112

/13-

01

TEMPERATURE (°C)

SUPP

LY C

URRE

NT (µ

A)

-20 20 60 100

160

140

OUTPUT CODE = FULL SCALECLOAD = 10pF

VDD = 5.5V

VDD = 4.5V

10

0-60 140

SHUTDOWN SUPPLY CURRENTvs. TEMPERATURE

2

8 MAX

1112

/13-

02

TEMPERATURE (°C)

SHUT

DOW

N SU

PPLY

CUR

RENT

(µA)

-20 20 60 100

6

4

SHDN = DGND

0.3

-0.30 256

DIFFERENTIAL NONLINEARITYvs. CODE

-0.2

0.2

0.1

MAX

1112

/13-

03

DIGITAL CODE

DNL

(LSB

)

64 128 192

0

-0.1

0.6

0-60 140

OFFSET ERROR vs. TEMPERATURE

0.1

0.2

0.5

MAX

1112

/13-

04

TEMPERATURE (°C)

OFFS

ET E

RROR

(LSB

)

-20 20 60 100

0.4

0.3

0.20

-0.200 256

INTEGRAL NONLINEARITYvs. CODE

-0.10

-0.15

0.15

0.10

0.05

MAX

1112

/13-

05

DIGITAL CODE

INL

(LSB

)

64 128 192

0

-0.05

20

-1000 25

FFT PLOT

-80

-20

0

MAX

1112

/13-

06

FREQUENCY (kHz)

AMPL

ITUD

E (d

B)

5 10 15 20

-60

-40

fCH_ = 10.034kHz, 4Vp-pfSAMPLE = 50ksps

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Pin Description

16 SSTRB

Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1112/MAX1113 begin the A/D conversion and goes high when the conversion is complete. In external clock mode, SSTRB pulses high for two clock periods before the MSB isshifted out. High impedance when CS is high (external clock mode only).

20 VDD Positive Supply Voltage, +4.5V to +5.5V

18 CSActive-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS ishigh, DOUT is high impedance.

19 SCLKSerial-Clock Input. Clocks data in and out of serial interface. In external clock mode,SCLK also sets the conversion speed (duty cycle must be 45% to 55%).

17 DIN Serial-Data Input. Data is clocked in at SCLK’s rising edge.

12 REFOUT Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND.

14 DGND Digital Ground

15 DOUTSerial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance whenCS is high.

13 AGND Analog Ground

10 SHDNThree-Level Shutdown Input. Normally floats. Pulling SHDN low shuts the MAX1112/MAX1113 down to 10µA (max) supply current; otherwise, the devices are fully opera-tional. Pulling SHDN high shuts down the internal reference.

11 REFINReference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to usethe internal reference.

5–8 CH4–CH7 Sampling Analog Inputs

1–4 CH0–CH3 Sampling Analog Inputs

+5V

3k

CLOAD

DGND

DOUT

CLOAD

DGND

3k

DOUT

a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL

Figure 1. Load Circuits for Enable Time

+5V

3k

CLOAD

DGND

DOUT

CLOAD

DGND

3k

DOUT

a) VOH to High-Z b) VOL to High-Z

Figure 2. Load Circuits for Disable Time

12

16

14

15

13

8

10

11

9

6

7

—

1–4

59 COMGround Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.Must be stable to ±0.5LSB.

PIN

MAX1113NAME FUNCTION

MAX1112

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_______________Detailed DescriptionThe MAX1112/MAX1113 analog-to-digital converters(ADCs) use a successive-approximation conversiontechnique and input track/hold (T/H) circuitry to convertan analog signal to an 8-bit digital output. A flexible seri-al interface provides easy interface to microprocessors(µPs). Figure 3 shows the Typical Operating Circuit.

Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-parator is illustrated in Figure 4, the equivalent input cir-cuit. In single-ended mode, IN+ is internally switched tothe selected input channel, CH_, and IN- is switched toCOM. In differential mode, IN+ and IN- are selectedfrom the fol lowing pairs: CH0/CH1, CH2/CH3,CH4/CH5, and CH6/CH7. Configure the MAX1112channels with Table 1 and the MAX1113 channels withTable 2.

In differential mode, IN- and IN+ are internally switchedto either of the analog inputs. This configuration ispseudo-differential to the effect that only the signal atIN+ is sampled. The return side (IN-) must remain sta-ble within ±0.5LSB (±0.1LSB for best results) withrespect to AGND during a conversion. To accomplishthis, connect a 0.1µF capacitor from IN- (the selectedanalog input) to AGND if necessary.

During the acquisition interval, the channel selected asthe positive input (IN+) charges capacitor CHOLD. The

acquisition interval spans two SCLK cycles and endson the falling SCLK edge after the last bit of the inputcontrol word has been entered. At the end of the acqui-sition interval, the T/H switch opens, retaining chargeon CHOLD as a sample of the signal at IN+.

The conversion interval begins with the input multiplex-er switching CHOLD from the positive input (IN+) to thenegative input (IN-). In single-ended mode, IN- is sim-ply COM. This unbalances node ZERO at the input ofthe comparator. The capacitive DAC adjusts during theremainder of the conversion cycle to restore nodeZERO to 0V within the limits of 8-bit resolution. Thisaction is equivalent to transferring a charge of 18pF x(VIN+ - VIN-) from CHOLD to the binary-weighted capac-itive DAC, which in turn forms a digital representation ofthe analog input signal.

Track/HoldThe T/H enters its tracking mode on the falling clockedge after the sixth bit of the 8-bit control byte hasbeen shifted in. It enters its hold mode on the fallingclock edge after the eighth bit of the control byte hasbeen shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the con-verter samples the “+” input; if it is set up for differentialinputs, IN- connects to the “-” input, and the difference(IN+ - IN-) is sampled. At the end of the conversion, thepositive input connects back to IN+, and CHOLDcharges to the input signal.

VDD

I/OSCK (SK)MOSI (SO)MISO (SI)

VSSSHDN

SSTRB

DOUTDIN

SCLKCS

COMDGNDAGND

VDD

CH7

1µF

0.1µF 1µFCH0

ANALOGINPUTS

MAX1112MAX1113

CPU

+5V

REFIN

REFOUT

Figure 3. Typical Operating Circuit

CH0CH1

CH2CH3

CH4*CH5*

CH6*CH7*COM

CSWITCH

TRACK

T/HSWITCH

CHOLD

HOLD

CAPACITIVE DACREFIN

ZERO

COMPARATOR

– +

18pF6.5k RIN

SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*.*MAX1112 ONLY

AT THE SAMPLING INSTANT,THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.

INPUTMUX

Figure 4. Equivalent Input Circuit

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Table 1a. MAX1112 Channel Selection in Single-Ended Mode (SGL/DIF = 1)

Table 1b. MAX1112 Channel Selection in Differential Mode (SGL/DIF = 0)

Table 2a. MAX1113 Channel Selection in Single-Ended Mode (SGL/DIF = 1)

Table 2b. MAX1113 Channel Selection in Differential Mode (SGL/DIF = 0)

–+111

–+1

CH2

10

–+0

CH3

11

–+0

CH1

10

+ –1

+

CH0

01

+ –100

+ –001

–

COMCH7CH6SEL2 CH5CH4

000

SEL0SEL1

+–111

+–0

CH2

11

– +1

CH3

01

+–0

–

CH1

01

–+1

+

CH0

10

–+010

+ –100

CH7CH6SEL2 CH5CH4

000

SEL0SEL1

+X11

+X

CH1

10

+

CH0

+X01

SEL2 CH3CH2

X00

SEL0SEL1

+–X11

+–X

–

CH1

01

+

CH0

–+X10

SEL2 CH3CH2

X00

SEL0SEL1

–

–

–

–

COM

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Table 3. Control-Byte Format

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0(MSB) (LSB)

NAME

SGL/DIF2

BIT

1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended mode, input signal voltages are referred to COM. In differential mode, the voltage differ-ence between two channels is measured. See Tables 1 and 2.

DESCRIPTION

UNI/BIP3

START

1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode (Table 4).

PD00 (LSB)

7 (MSB)

1 = external clock mode, 0 = internal clock mode.Selects external or internal clock mode.

The first logic “1” bit after CS goes low defines the beginning of the control byte.

SEL2SEL1SEL0

654

Select which of the input channels are to be used for the conversion (Tables 1 and 2).

PD111 = fully operational, 0 = power-down.Selects fully operational or power-down mode.

The time required for the T/H to acquire an input signalis a function of how quickly its input capacitance ischarged. If the input signal’s source impedance is high,the acquisition time lengthens, and more time must beallowed between conversions. The acquisition time,tACQ, is the minimum time needed for the signal to beacquired. It is calculated by:

tACQ = 6 x (RS + RIN) x 18pF

where RIN = 6.5kΩ, RS = the source impedance of theinput signal, and tACQ is never less than 1µs. Note thatsource impedances below 2.4kΩ do not significantlyaffect the AC performance of the ADC.

Input BandwidthThe ADC’s input tracking circuitry has a 1.5MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADC’s sampling rate byusing undersampling techniques. To avoid high-frequency signals being aliased into the frequencyband of interest, anti-alias filtering is recommended.

Analog InputsInternal protection diodes, which clamp the analoginput to VDD and AGND, allow the channel input pins toswing from (AGND - 0.3V) to (VDD + 0.3V) without dam-

age. However, for accurate conversions near full scale,the inputs must not exceed VDD by more than 50mV orbe lower than AGND by 50mV.

If the analog input exceeds 50mV beyond the sup-plies, do not forward bias the protection diodes ofoff channels over 2mA.

The MAX1112/MAX1113 can be configured for differen-tial or single-ended inputs with bits 2 and 3 of the con-trol byte (Table 3). In single-ended mode, analog inputsare internally referenced to COM with a full-scale inputrange from COM to VREFIN + COM. For bipolar opera-tion, set COM to VREFIN / 2.

In differential mode, choosing unipolar mode sets thedifferential input range at 0V to VREFIN. In unipolarmode, the output code is invalid (code zero) when anegative differential input voltage is applied. Bipolarmode sets the differential input range to ±VREFIN / 2.Note that in this mode, the common-mode input rangeincludes both supply rails. Refer to Table 4 for inputvoltage ranges.

Quick LookTo quickly evaluate the MAX1112/MAX1113’s analogperformance, use the circuit of Figure 5. TheMAX1112/MAX1113 require a control byte to be writtento DIN before each conversion. Tying DIN to +5V feeds

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in control bytes of $FF (hex), which trigger single-ended, unipolar conversions on CH7 (MAX1112) orCH3 (MAX1113) in external clock mode without power-ing down between conversions. In external clock mode,the SSTRB output pulses high for two clock periodsbefore the most significant bit (MSB) of the 8-bit con-version result is shifted out of DOUT. Varying the ana-log input alters the output code. A total of 10 clockcycles is required per conversion. All transitions of theSSTRB and DOUT outputs occur on SCLK’s fallingedge.

How to Start a ConversionA conversion is started by clocking a control byte intoDIN. With CS low, each rising edge on SCLK clocks a bit

from DIN into the MAX1112/MAX1113’s internal shift reg-ister. After CS falls, the first arriving logic “1” bit at DINdefines the MSB of the control byte. Until this first start bitarrives, any number of logic “0” bits can be clocked intoDIN with no effect. Table 3 shows the control-byte format.

The MAX1112/MAX1113 are compatible withMICROWIRE, SPI, and QSPI devices. For SPI, select thecorrect clock polarity and sampling edge in the SPI con-trol registers: set CPOL = 0 and CPHA = 0. MICROWIRE,SPI, and QSPI all transmit a byte and receive a byte at thesame time. Using the Typical Operating Circuit (Figure 3),the simplest software interface requires three 8-bit trans-fers to perform a conversion (one 8-bit transfer to config-ure the ADC, and two more 8-bit transfers to clock out the

1µF0.1µF

VDD

DGND

AGND

CS

SCLK

DIN

DOUT

SSTRB

SHDN

+5V

N.C.

0.01µFCH7 (CH3)

COM

REFOUT

REFINC11µF

0V TO+4.096VANALOG

INPUT

OSCILLOSCOPE

CH1 CH2 CH3 CH4

*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FF (HEX)

( ) ARE FOR THE MAX1113.

MAX1112MAX1113

+5V

500kHzOSCILLATOR

SCLK

SSTRB

DOUT*

Figure 5. Quick-Look Circuit

Table 4. Full-Scale and Zero-Scale Voltages

UNIPOLAR MODE

VREFIN + COM +VREFIN / 2+ COM

Full Scale

COM COM -VREFIN / 2+ COM

PositiveFull ScaleZero Scale Zero

Scale

BIPOLAR MODE

NegativeFull Scale

8-bit conversion result). Figure 6 shows the MAX1112/MAX1113 common serial-interface connections.

Simple Software InterfaceMake sure the CPU’s serial interface runs in mastermode so the CPU generates the serial clock. Choose aclock frequency from 50kHz to 500kHz.

1) Set up the control byte for external clock mode andcall it TB1. TB1 should be of the format 1XXXXX11binary, where the Xs denote the particular channeland conversion mode selected.

2) Use a general-purpose I/O line on the CPU to pullCS low.

3) Transmit TB1 and, simultaneously, receive a byteand call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simulta-neously, receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and, simulta-neously, receive byte RB3.

6) Pull CS high.

Figure 7 shows the timing for this sequence. Bytes RB2and RB3 contain the result of the conversion paddedwith two leading zeros and six trailing zeros. The totalconversion time is a function of the serial-clock frequency and the amount of idle time between 8-bittransfers. Make sure that the total conversion time doesnot exceed 1ms, to avoid excessive T/H droop.

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12 ______________________________________________________________________________________

SSTRB

CS

SCLK

DIN

DOUT

1 4 8 12 16 20 24

START

SEL2 SEL1 SEL0 UNI/BIP

SGL/DIF PD1 PD0

B7 B6 B5 B4 B3 B2 B1 B0

ACQUISITION

(fSCLK = 500kHz)

IDLE

FILLED WITH ZEROS

IDLECONVERSION

tACQ

A/D STATE

RB1 RB2 RB3

4µs

Figure 7. Single-Conversion Timing, External Clock Mode, 24 Clocks

CS

SCLK

DOUT

I/O

SCK

MISO+5V

SS

a) SPI

CS

SCLK

DOUT

CS

SCK

MISO+5V

SS

b) QSPI

MAX1112MAX1113

MAX1112MAX1113

MAX1112MAX1113

CS

SCLK

DOUT

I/O

SK

SI

c) MICROWIRE

Figure 6. Common Serial-Interface Connections to theMAX1112/MAX1113

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______________________________________________________________________________________ 13

Digital OutputIn unipolar input mode, the output is straight binary(Figure 15). For bipolar inputs, the output is two’s-com-plement (Figure 16). Data is clocked out at SCLK’sfalling edge in MSB-first format.

Clock ModesThe MAX1112/MAX1113 can use either an external ser-ial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, theexternal clock shifts data in and out of the devices. BitPD0 of the control byte programs the clock mode.Figures 8–11 show the timing characteristics commonto both modes.

External ClockIn external clock mode, the external clock not onlyshifts data in and out, it also drives the analog-to-digital

conversion steps. SSTRB pulses high for two clockperiods after the last bit of the control byte. Successive-approximation bit decisions are made and appear atDOUT on each of the next eight SCLK falling edges(Figure 7). After the eight data bits are clocked out,subsequent clock pulses clock out zeros from theDOUT pin.

SSTRB and DOUT go into a high-impedance statewhen CS goes high; after the next CS falling edge,SSTRB outputs a logic low. Figure 9 shows the SSTRBtiming in external clock mode.

The conversion must complete in 1ms, or droop on thesample-and-hold capacitors may degrade conversionresults. Use internal clock mode if the serial-clock fre-quency is less than 50kHz, or if serial-clock interruptionscould cause the conversion interval to exceed 1ms.

• • •

• • •

• • •

• • •

CS

SCLK

DIN

DOUT

tCSStCL

tDS

tDH

tDV tDO

tCH

tDO tTR

tCSH

Figure 8. Detailed Serial-Interface Timing

• • •

• • • • • •

• • • •

• • •

tSDV

tSSTRB

PD0 CLOCKED IN

tSTR

SSTRB

SCLK

CS

tSSTRB

• • • •

Figure 9. External Clock Mode SSTRB Detailed Timing

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14 ______________________________________________________________________________________

SSTRB

CS

SCLK

DIN

DOUT

1 4 8 12 15 17

START

SEL2 SEL1 SEL0 UNI/BIP

SGL/DIF PD1 PD0

B7 B6 B1 B0

tACQ4µs (fSCLK = 500kHz)

IDLE

FILLED WITH ZEROS

IDLECONVERSION

25µs TYPA/D STATE

2 3 5 6 7 9 10 11 16 18

tCONV

Figure 10. Internal Clock Mode Timing

PD0 CLOCK IN

tSSTRB

tCSH

tCONVtSCK

SSTRB

SCLK

tCSS

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

CS

Figure 11. Internal Clock Mode SSTRB Detailed Timing

Internal ClockInternal clock mode frees the µP from the burden ofrunning the SAR conversion clock. This allows the con-version results to be read back at the processor’s con-venience, at any clock rate up to 2MHz. SSTRB goeslow at the start of the conversion and then goes highwhen the conversion is complete. SSTRB is low for25µs (typically), during which time SCLK should remainlow for best noise performance.

An internal register stores data when the conversion isin progress. SCLK clocks the data out of this register atany time after the conversion is complete. After SSTRBgoes high, the second falling clock edge produces theMSB of the conversion at DOUT, followed by the

remaining bits in MSB-first format (Figure 10). CS doesnot need to be held low once a conversion is started.Pulling CS high prevents data from being clocked intothe MAX1112/MAX1113 and three-states DOUT, but itdoes not adversely affect an internal clock-mode con-version already in progress. When internal clock modeis selected, SSTRB does not go into a high-impedancestate when CS goes high.

Figure 11 shows the SSTRB timing in internal clockmode. In this mode, data can be shifted in and out ofthe MAX1112/MAX1113 at clock rates up to 2MHz, pro-vided that the minimum acquisition time, tACQ, is keptabove 1µs.

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______________________________________________________________________________________ 15

SCLK

DIN

DOUT

CS

S CONTROL BYTE 0 CONTROL BYTE 1S

CONVERSION RESULT 0

B7 B0 B7 B0 B7

CONVERSION RESULT 1 CONVERSION RESULT 2SSTRB

CONTROL BYTE 2S

1 8 8 810 1 10 1 10 1

CONTROL BYTE 3S

Figure 12a. Continuous Conversions, External Clock Mode, 10 Clocks/Conversion Timing

CS

SCLK

DIN

DOUT

S CONTROL BYTE 0 CONTROL BYTE 1S

CONVERSION RESULT 0

B7 B0 B7

CONVERSION RESULT 1

Figure 12b. Continuous Conversions, External Clock Mode, 16 Clocks/Conversion Timing

Data FramingThe falling edge of CS does not start a conversion. Thefirst logic high clocked into DIN is interpreted as a startbit and defines the first bit of the control byte. A conver-sion starts on the falling edge of SCLK, after the eighthbit of the control byte (the PD0 bit) is clocked into DIN.The start bit is defined as:

The first high bit clocked into DIN with CS low anytime the converter is idle, e.g., after VDD is applied.

OR

The first high bit clocked into DIN after the MSB of aconversion in progress is clocked onto the DOUTpin.

If CS is toggled before the current conversion is com-plete, then the next high bit clocked into DIN is recog-nized as a start bit; the current conversion isterminated, and a new one is started.

The fastest the MAX1112/MAX1113 can run is 10clocks per conversion. Figure 12a shows the serial-interface timing necessary to perform a conversionevery 10 SCLK cycles in external clock mode.

Many microcontrollers require that conversions occur inmultiples of eight SCLK clocks; 16 clocks per conver-sion is typically the fastest that a microcontroller candrive the MAX1112/MAX1113. Figure 12b shows theserial-interface timing necessary to perform a conver-sion every 16 SCLK cycles in external clock mode.

__________Applications InformationPower-On Reset

When power is first applied, and if SHDN is not pulledlow, internal power-on reset circuitry activates theMAX1112/MAX1113 in internal clock mode. SSTRB ishigh on power-up and, if CS is low, the first logical 1 onDIN is interpreted as a start bit. Until a conversion takesplace, DOUT shifts out zeros. No conversions shouldbe performed until the reference voltage has stabilized(see the Wakeup Time specifications in the TimingCharacteristics).

Power-DownWhen operating at speeds below the maximum sam-pling rate, the MAX1112/MAX1113’s automatic power-down mode can save considerable power by placingthe converters in a low-current shutdown state betweenconversions. Figure 13 shows the average supply cur-rent as a function of the sampling rate.

Select power-down with PD1 of the DIN control bytewith SHDN high or floating (Table 3). Pull SHDN low atany time to shut down the converters completely. SHDNoverrides PD1 of the control byte. Figures 14a and 14billustrate the various power-down sequences in bothexternal and internal clock modes.

Software Power-DownSoftware power-down is activated using bit PD1 of thecontrol byte. When software power-down is asserted, theADCs continue to operate in the last specified clockmode until the conversion is complete. The ADCs thenpower down into a low quiescent-current state. In internalclock mode, the interface remains active, and conversionresults may be clocked out after the MAX1112/MAX1113 have entered a software power-down.

The first logical 1 on DIN is interpreted as a start bit,which powers up the MAX1112/MAX1113. If the DIN bytecontains PD1 = 1, then the chip remains powered up. IfPD1 = 0, power-down resumes after one conversion.

Hard-Wired Power-DownPulling SHDN low places the converters in hard-wiredpower-down. Unlike software power-down, the conver-sion is not completed; it stops coincidentally with SHDNbeing brought low. SHDN also controls the state of theinternal reference (Table 5). Letting SHDN float enablesthe internal 4.096V voltage reference. When returning tonormal operation with SHDN floating, there is a tRCdelay of approximately 1MΩ x CLOAD, where CLOAD isthe capacitive loading on the SHDN pin. Pulling SHDNhigh disables the internal reference, which saves powerwhen using an external reference.

External ReferenceAn external reference between 1V and VDD should beconnected directly at the REFIN terminal. The DC inputimpedance at REFIN is extremely high, consisting ofleakage current only (typically 10nA). During a conver-sion, the reference must be able to deliver up to 20µAaverage load current and have an output impedance of1kΩ or less at the conversion clock frequency. If thereference has higher output impedance or is noisy,bypass it close to the REFIN pin with a 0.1µF capacitor.

If an external reference is used with the MAX1112/MAX1113, tie SHDN to VDD to disable the internal refer-ence and decrease power consumption.

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16 ______________________________________________________________________________________

Table 5. Hard-Wired Power-Down andInternal Reference State

SHDNSTATE

DEVICE MODE

1 Enabled

Floating Enabled

0 Power-Down

INTERNALREFERENCE

Disabled

Disabled

Enabled

1000

100 10 30 50

100

MAX

1112

/13-

fig13

SAMPLING RATE (ksps)

SUPP

LY C

URRE

NT (µ

A)

20 40

VDD = VREFIN = 5VCLOAD AT DOUT + SSTRB

CLOAD = 30pFCODE = 11111111



Figure 13. Average Supply Current vs. Sampling Rate

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______________________________________________________________________________________ 17

Internal ReferenceTo use the MAX1112/MAX1113 with the internal refer-ence, connect REFIN to REFOUT. The full-scale rangeof the MAX1112/MAX1113 with the internal reference istypically 4.096V with unipolar inputs, and ±2.048V withbipolar inputs. The internal reference should bebypassed to AGND with a 1µF capacitor placed asclose to the REFIN pin as possible.

Transfer FunctionTable 4 shows the full-scale voltage ranges for unipolarand bipolar modes. Figure 15 depicts the nominal,unipolar I/O transfer function, and Figure 16 shows thebipolar I/O transfer function when using a 4.096V refer-ence. Code transitions occur at integer LSB values.Output coding is binary, with 1LSB = 16mV(4.096V/256) for unipolar operation and 1LSB = 16mV[(4.096V/2 - -4.096V/2)/256] for bipolar operation.

POWERED UP POWER-DOWN

POWEREDUPPOWERED UP

DATA VALID DATA VALID DATA INVALID

EXTERNALEXTERNALINTERNAL

S X X X X X 1 1 S 0 1X XXXX X X X X XS 1 1

POWER-DOWNMODE

DOUT

DIN

CLOCKMODE

SHDN

SETS EXTERNALCLOCK MODE

SETS EXTERNALCLOCK MODE

SETS POWER-DOWN MODE

Figure 14a. Power-Down Modes, External Clock Timing Diagram

POWER-DOWNPOWERED

UP

POWERED UP

DATA VALID DATA VALID

INTERNAL CLOCK MODE

S X X X X X 1 0 S 0 0X XXXX S

MODE

DOUT

DIN

SETS INTERNALCLOCK MODE

SETS POWER-DOWN MODE

CONVERSIONCONVERSIONSSTRB

Figure 14b. Power-Down Modes, Internal Clock Timing Diagram

Layout, Grounding, and BypassingFor best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layoutshould ensure that digital and analog signal lines areseparated from each other. Do not run analog and digi-tal (especially clock) lines parallel to one another, ordigital lines underneath the ADC package.

Figure 17 shows the recommended system groundconnections. A single-point analog ground (star groundpoint) should be established at AGND, separate fromthe logic ground. Connect all other analog grounds andDGND to the star ground. No other digital systemground should be connected to this ground. Theground return to the power supply for the star groundshould be low impedance and as short as possible fornoise-free operation.

High-frequency noise in the VDD power supply mayaffect the comparator in the ADC. Bypass the supply tothe star ground with 0.1µF and 1µF capacitors close tothe VDD pin of the MAX1112/MAX1113. Minimizecapacitor lead lengths for best supply-noise rejection. Ifthe +5V power supply is very noisy, a 10Ω resistor canbe connected to form a lowpass filter.

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18 ______________________________________________________________________________________

+5V GND

SUPPLIES

DGND+5VDGNDAGNDVDD

DIGITALCIRCUITRYMAX1112

MAX1113

R* = 10Ω

* OPTIONAL

Figure 17. Power-Supply Grounding Connections

01111111

OUTPUT CODE

01111110

00000010

00000001

00000000

11111111

11111110

11111101

10000001

10000000

-FS COM

INPUT VOLTAGE (LSB) +FS - 1

LSB 2

+FS = VREFIN + COM

2

-FS = -VREFIN + COM

2

COM = VREFIN 2

1LSB = VREFIN 256

Figure 16. Bipolar Transfer Function

OUTPUT CODEFULL-SCALETRANSITION

11111111

11111110

11111101

00000011

00000010

00000001

000000001 2 30 FS

FS - 1LSBINPUT VOLTAGE (LSB)(COM)

FS = VREFIN + COM VREFIN 2561LSB =

Figure 15. Unipolar Transfer Function

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______________________________________________________________________________________ 19

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

VDD

SCLK

CS

DINCH3

CH2

CH1

CH0

TOP VIEW

SSTRB

DOUT

DGND

AGNDCH7

CH6

CH5

CH4

12

11

9

10

REFOUT

REFINSHDN

COM

MAX1112

DIP/SSOP

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VDD

SCLK

CS

DIN

SSTRB

DOUT

DGND

AGND

CH0

CH1

CH2

CH3

COM

SHDN

REFIN

REFOUT

MAX1113

DIP/QSOP

Pin Configurations

___________________Chip InformationOrdering Information (continued)

PART

MAX1112EAP

MAX1112MJP -55°C to +125°C

-40°C to +85°C


20 SSOP

20 CERDIP**

**Contact factory for availability.

TRANSISTOR COUNT: 1996

SUBSTRATE CONNECTED TO DGNDMAX1112EPP -40°C to +85°C 20 Plastic DIP

MAX1113CPE

MAX1113EPE

MAX1113EEE -40°C to +85°C

-40°C to +85°C

0°C to +70°C 16 Plastic DIP

16 Plastic DIP

16 QSOP

MAX1113CEE 0°C to +70°C 16 QSOP

MAX1113MJE -55°C to +125°C 16 CERDIP**

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+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCs________________________________________________________Package Information

QS

OP

.EP

S

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

SS

OP

.EP

S


MAX233

cxxxvii

General DescriptionThe MAX220–MAX249 family of line drivers/receivers isintended for all EIA/TIA-232E and V.28/V.24 communica-tions interfaces, particularly applications where ±12V isnot available. These parts are especially useful in battery-powered sys-tems, since their low-power shutdown mode reducespower dissipation to less than 5µW. The MAX225,MAX233, MAX235, and MAX245/MAX246/MAX247 useno external components and are recommended for appli-cations where printed circuit board space is critical.

________________________ApplicationsPortable Computers

Low-Power Modems

Interface Translation

Battery-Powered RS-232 Systems

Multidrop RS-232 Networks

____________________________FeaturesSuperior to Bipolar Operate from Single +5V Power Supply

(+5V and +12V—MAX231/MAX239) Low-Power Receive Mode in Shutdown

(MAX223/MAX242) Meet All EIA/TIA-232E and V.28 Specifications Multiple Drivers and Receivers 3-State Driver and Receiver Outputs Open-Line Detection (MAX243)


Ordering Information continued at end of data sheet.*Contact factory for dice specifications.

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+5V-Powered, Multichannel RS-232Drivers/Receivers

________________________________________________________________ Maxim Integrated Products 1

Selection Table

19-4323; Rev 10; 8/01

PARTMAX220CPEMAX220CSEMAX220CWE 0°C to +70°C

0°C to +70°C0°C to +70°C

TEMP. RANGE PIN-PACKAGE16 Plastic DIP16 Narrow SO16 Wide SO

MAX220C/D 0°C to +70°C Dice*MAX220EPEMAX220ESEMAX220EWE -40°C to +85°C

-40°C to +85°C-40°C to +85°C 16 Plastic DIP

16 Narrow SO16 Wide SO

MAX220EJE -40°C to +85°C 16 CERDIPMAX220MJE -55°C to +125°C 16 CERDIP

Power No. of Nominal SHDN RxPart Supply RS-232 No. of Cap. Value & Three- Active in Data RateNumber (V) Drivers/Rx Ext. Caps (µF) State SHDN (kbps) FeaturesMAX220 +5 2/2 4 0.1 No — 120 Ultra-low-power, industry-standard pinoutMAX222 +5 2/2 4 0.1 Yes — 200 Low-power shutdownMAX223 (MAX213) +5 4/5 4 1.0 (0.1) Yes 120 MAX241 and receivers active in shutdownMAX225 +5 5/5 0 — Yes 120 Available in SOMAX230 (MAX200) +5 5/0 4 1.0 (0.1) Yes — 120 5 drivers with shutdownMAX231 (MAX201) +5 and 2/2 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies;

+7.5 to +13.2 same functions as MAX232MAX232 (MAX202) +5 2/2 4 1.0 (0.1) No — 120 (64) Industry standardMAX232A +5 2/2 4 0.1 No — 200 Higher slew rate, small capsMAX233 (MAX203) +5 2/2 0 — No — 120 No external capsMAX233A +5 2/2 0 — No — 200 No external caps, high slew rateMAX234 (MAX204) +5 4/0 4 1.0 (0.1) No — 120 Replaces 1488MAX235 (MAX205) +5 5/5 0 — Yes — 120 No external capsMAX236 (MAX206) +5 4/3 4 1.0 (0.1) Yes — 120 Shutdown, three stateMAX237 (MAX207) +5 5/3 4 1.0 (0.1) No — 120 Complements IBM PC serial portMAX238 (MAX208) +5 4/4 4 1.0 (0.1) No — 120 Replaces 1488 and 1489MAX239 (MAX209) +5 and 3/5 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies;

+7.5 to +13.2 single-package solution for IBM PC serial portMAX240 +5 5/5 4 1.0 Yes — 120 DIP or flatpack packageMAX241 (MAX211) +5 4/5 4 1.0 (0.1) Yes — 120 Complete IBM PC serial portMAX242 +5 2/2 4 0.1 Yes 200 Separate shutdown and enableMAX243 +5 2/2 4 0.1 No — 200 Open-line detection simplifies cablingMAX244 +5 8/10 4 1.0 No — 120 High slew rateMAX245 +5 8/10 0 — Yes 120 High slew rate, int. caps, two shutdown modesMAX246 +5 8/10 0 — Yes 120 High slew rate, int. caps, three shutdown modesMAX247 +5 8/9 0 — Yes 120 High slew rate, int. caps, nine operating modesMAX248 +5 8/8 4 1.0 Yes 120 High slew rate, selective half-chip enablesMAX249 +5 6/10 4 1.0 Yes 120 Available in quad flatpack package

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS—MAX220/222/232A/233A/242/243

ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)

Note 1: Input voltage measured with TOUT in high-impedance state, SHDN or VCC = 0V.Note 2: For the MAX220, V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage (VCC) ...............................................-0.3V to +6VInput VoltagesTIN..............................................................-0.3V to (VCC - 0.3V)RIN (Except MAX220) ........................................................±30VRIN (MAX220).....................................................................±25VTOUT (Except MAX220) (Note 1) .......................................±15VTOUT (MAX220)...............................................................±13.2V

Output VoltagesTOUT...................................................................................±15VROUT.........................................................-0.3V to (VCC + 0.3V)

Driver/Receiver Output Short Circuited to GND.........ContinuousContinuous Power Dissipation (TA = +70°C)16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW18-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW

20-Pin Plastic DIP (derate 8.00mW/°C above +70°C) ..440mW16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW18-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW20-Pin Wide SO (derate 10.00mW/°C above +70°C)....800mW20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW16-Pin CERDIP (derate 10.00mW/°C above +70°C).....800mW18-Pin CERDIP (derate 10.53mW/°C above +70°C).....842mW

Operating Temperature RangesMAX2_ _AC_ _, MAX2_ _C_ _.............................0°C to +70°CMAX2_ _AE_ _, MAX2_ _E_ _ ..........................-40°C to +85°CMAX2_ _AM_ _, MAX2_ _M_ _.......................-55°C to +125°C


V1.4 0.8Input Logic Threshold Low

UNITSMIN TYP MAXPARAMETER CONDITIONS

Input Logic Threshold HighAll devices except MAX220 2 1.4

V

All except MAX220, normal operation 5 40Logic Pull-Up/lnput Current

SHDN = 0V, MAX222/242, shutdown, MAX220 ±0.01 ±1µA

VCC = 5.5V, SHDN = 0V, VOUT = ±15V, MAX222/242 ±0.01 ±10Output Leakage Current

VCC = SHDN = 0V, VOUT = ±15V ±0.01 ±10µA

200 116Data Rate kb/s

Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 10M ΩOutput Short-Circuit Current VOUT = 0V ±7 ±22 mA

RS-232 Input Voltage Operating Range ±30 V

All except MAX243 R2IN 0.8 1.3RS-232 Input Threshold Low VCC = 5V

MAX243 R2IN (Note 2) -3V

All except MAX243 R2IN 1.8 2.4RS-232 Input Threshold High VCC = 5V

MAX243 R2IN (Note 2) -0.5 -0.1V

All except MAX243, VCC = 5V, no hysteresis in shdn. 0.2 0.5 1RS-232 Input Hysteresis

MAX243 1V

RS-232 Input Resistance 3 5 7 kΩTTL/CMOS Output Voltage Low IOUT = 3.2mA 0.2 0.4 V

TTL/CMOS Output Voltage High IOUT = -1.0mA 3.5 VCC - 0.2 V

Sourcing VOUT = GND -2 -10mATTL/CMOS Output Short-Circuit Current

Shrinking VOUT = VCC 10 30

V±5 ±8Output Voltage Swing All transmitter outputs loaded with 3kΩ to GND

RS-232 TRANSMITTERS

RS-232 RECEIVERS

2.4MAX220: VCC = 5.0V

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_______________________________________________________________________________________ 3

Note 3: MAX243 R2OUT is guaranteed to be low when R2IN is ≥ 0V or is floating.

ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued)(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)

Operating Supply Voltage

SHDN Threshold High

4.5 5.5 V

MAX222/242

Transmitter-Output Enable Time (SHDN goes high), Figure 4

2.0 1.4 V

MAX220 0.5 2

tET

No loadMAX222/232A/233A/242/243 4 10

MAX222/232A/233A/242/243 6 12 30

MAX220 12VCC Supply Current (SHDN = VCC),Figures 5, 6, 11, 19 3kΩ load

both inputs MAX222/232A/233A/242/243 15

mA

Transition Slew Rate

TA = +25°C 0.1 10

CL = 50pF to 2500pF, RL = 3kΩ to 7kΩ, VCC = 5V, TA = +25°C,measured from +3V to -3V or -3V to +3V

TA = 0°C to +70°C

CONDITIONS

2 50

MAX220 1.5 3 30

V/µs

TA = -40°C to +85°C 2 50

MAX222/242, 0.1µF caps(includes charge-pump start-up)

Shutdown Supply Current MAX222/242

TA = -55°C to +125°C 35 100

µA

SHDN Input Leakage Current MAX222/242 ±1 µA

SHDN Threshold Low MAX222/242 1.4 0.8 V

250

MAX222/232A/233A/242/243 1.3 3.5

µs

tPHLTMAX220 4 10

Transmitter-Output Disable Time (SHDN goes low), Figure 4

tDT

MAX222/232A/233A/242/243 1.5 3.5

Transmitter Propagation DelayTLL to RS-232 (normal operation), Figure 1 tPLHT

MAX220 5 10

µs

V2.0 1.4

MAX222/242, 0.1µF caps

µA±0.05 ±10

600

TTL/CMOS Output Leakage Current

EN Input Threshold High

MAX222/232A/233A/242/243 0.5 1

ns

tPHLRMAX220 0.6 3

tPLHRMAX222/232A/233A/242/243 0.6 1

Receiver Propagation DelayRS-232 to TLL (normal operation),Figure 2

tPHLT - tPLHT

MAX220 0.8 3

µs

MAX222/232A/233A/242/243

tPHLS MAX242 0.5 10Receiver Propagation Delay RS-232 to TLL (shutdown), Figure 2 tPLHS MAX242 2.5 10

µs

Receiver-Output Enable Time, Figure 3 tER MAX242

UNITSMIN TYP MAX

125 500

PARAMETER

MAX242

ns

SHDN = VCC or EN = VCC (SHDN = 0V for MAX222),0V ≤ VOUT ≤ VCC

Receiver-Output Disable Time, Figure 3 tDR MAX242 160 500 ns

300ns

Transmitter + to - Propagation Delay Difference (normal operation) MAX220 2000

tPHLR - tPLHRMAX222/232A/233A/242/243 100

nsReceiver + to - Propagation Delay Difference (normal operation) MAX220 225

V1.4 0.8EN Input Threshold Low MAX242

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4 _______________________________________________________________________________________

__________________________________________Typical Operating Characteristics

MAX220/MAX222/MAX232A/MAX233A/MAX242/MAX243

10

8

-100 5 15 25

OUTPUT VOLTAGE vs. LOAD CURRENT

-4

-6

-8

-2

6

4

2

MAX

220-

01

LOAD CURRENT (mA)

OUTP

UT V

OLTA

GE (V

)

10

0

20

0.1µF

EITHER V+ OR V- LOADED

VCC = ±5VNO LOAD ONTRANSMITTER OUTPUTS(EXCEPT MAX220, MAX233A)

V- LOADED, NO LOAD ON V+

V+ LOADED, NO LOAD ON V-

1µF

1µF0.1µF

11

10

40 10 40 60

AVAILABLE OUTPUT CURRENTvs. DATA RATE

6

5

7

9

8

MAX

220-

02

DATA RATE (kbits/sec)

OUTP

UT C

URRE

NT (m

A)

20 30 50

OUTPUT LOAD CURRENTFLOWS FROM V+ TO V-

VCC = +5.25V

ALL CAPS1µF

ALL CAPS0.1µF

VCC = +4.75V

+10V

-10V

MAX222/MAX242ON-TIME EXITING SHUTDOWN

+5V+5V

0V

0V

MAX

220-

03

500µs/div

V+, V

- VOL

TAGE

(V)

1µF CAPSV+

V+

V-V-

SHDN

0.1µF CAPS

1µF CAPS

0.1µF CAPS

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_______________________________________________________________________________________ 5

VCC...........................................................................-0.3V to +6VV+................................................................(VCC - 0.3V) to +14VV- ............................................................................+0.3V to -14VInput VoltagesTIN ............................................................-0.3V to (VCC + 0.3V)RIN......................................................................................±30V

Output VoltagesTOUT ...................................................(V+ + 0.3V) to (V- - 0.3V)ROUT.........................................................-0.3V to (VCC + 0.3V)

Short-Circuit Duration, TOUT ......................................ContinuousContinuous Power Dissipation (TA = +70°C)14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)....800mW16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW24-Pin Narrow Plastic DIP

(derate 13.33mW/°C above +70°C) ..........1.07W24-Pin Plastic DIP (derate 9.09mW/°C above +70°C)......500mW16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW

20-Pin Wide SO (derate 10 00mW/°C above +70°C).......800mW24-Pin Wide SO (derate 11.76mW/°C above +70°C).......941mW28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W44-Pin Plastic FP (derate 11.11mW/°C above +70°C) .....889mW14-Pin CERDIP (derate 9.09mW/°C above +70°C) ..........727mW16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW24-Pin Narrow CERDIP

(derate 12.50mW/°C above +70°C) ..............1W24-Pin Sidebraze (derate 20.0mW/°C above +70°C)..........1.6W28-Pin SSOP (derate 9.52mW/°C above +70°C).............762mW

Operating Temperature RangesMAX2 _ _ C _ _......................................................0°C to +70°CMAX2 _ _ E _ _ ...................................................-40°C to +85°CMAX2 _ _ M _ _ ...............................................-55°C to +125°C


ABSOLUTE MAXIMUM RATINGS—MAX223/MAX230–MAX241

ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

CONDITIONS MIN TYP MAX UNITS

Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground ±5.0 ±7.3 V

VCC Power-Supply CurrentNo load,TA = +25°C

5 10

mA7 15

0.4 1

V+ Power-Supply Current1.8 5

mA5 15

Shutdown Supply Current TA = +25°C15 50

VInput Logic Threshold High

TIN 2.0

EN, SHDN (MAX223);EN, SHDN (MAX230/235/236/240/241)

2.4

Logic Pull-Up Current TIN = 0V 1.5 200

Receiver Input VoltageOperating Range

-30 30 V

µA

µA1 10

VInput Logic Threshold Low TIN; EN, SHDN (MAX233); EN, SHDN (MAX230/235–241) 0.8

MAX231/239

MAX223/230/234–238/240/241

MAX232/233

PARAMETER

MAX239

MAX230/235/236/240/241

MAX231

MAX223

mA

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6 _______________________________________________________________________________________

V

0.8 1.2

PARAMETER MIN TYP MAX UNITSCONDITIONS

Normal operationSHDN = 5V (MAX223)SHDN = 0V (MAX235/236/240/241)

1.7 2.4

RS-232 Input Threshold LowTA = +25°C, VCC = 5V

0.6 1.5

VRS-232 Input Threshold HighTA = +25°C,VCC = 5V Shutdown (MAX223)

SHDN = 0V,EN = 5V (R4IN‚ R5IN)

1.5 2.4

ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241 (continued)(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)

Shutdown (MAX223)SHDN = 0V,EN = 5V (R4IN, R5IN)

Normal operationSHDN = 5V (MAX223)SHDN = 0V (MAX235/236/240/241)

RS-232 Input Hysteresis VCC = 5V, no hysteresis in shutdown 0.2 0.5 1.0 V

RS-232 Input Resistance TA = +25°C, VCC = 5V 3 5 7 kΩ

TTL/CMOS Output Voltage Low IOUT = 1.6mA (MAX231/232/233, IOUT = 3.2mA) 0.4 V

TTL/CMOS Output Voltage High IOUT = -1mA 3.5 VCC - 0.4 V

TTL/CMOS Output Leakage Current0V ≤ ROUT ≤ VCC; EN = 0V (MAX223); EN = VCC (MAX235–241 )

0.05 ±10 µA

MAX223 600nsReceiver Output Enable Time

Normal operation MAX235/236/239/240/241 400

MAX223 900nsReceiver Output Disable Time

Normal operation MAX235/236/239/240/241 250

Normal operation 0.5 10

µsSHDN = 0V(MAX223)

4 40Propagation DelayRS-232 IN toTTL/CMOS OUT,CL = 150pF 6 40

3 5.1 30

V/µsMAX231/MAX232/MAX233, TA = +25°C, VCC = 5V, RL = 3kΩ to 7kΩ, CL = 50pF to 2500pF, measured from+3V to -3V or -3V to +3V

4 30

Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 Ω

Transmitter Output Short-CircuitCurrent

±10 mA

tPHLS

tPLHS

Transition Region Slew Rate

MAX223/MAX230/MAX234–241, TA = +25°C, VCC = 5V, RL = 3kΩ to 7kΩ‚ CL = 50pF to 2500pF, measured from+3V to -3V or -3V to +3V

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8.5

6.54.5 5.5

TRANSMITTER OUTPUTVOLTAGE (VOH) vs. VCC

7.0

8.0

MAX

220-

04

VCC (V)

V OH

(V)

5.0

7.5

1 TRANSMITTERLOADED

3 TRANS-MITTERSLOADED

4 TRANSMITTERSLOADED

2 TRANSMITTERSLOADED

TA = +25°CC1–C4 = 1µFTRANSMITTERLOADS =3kΩ || 2500pF

7.4

6.00 2500

TRANSMITTER OUTPUT VOLTAGE (VOH)vs. LOAD CAPACITANCE AT

DIFFERENT DATA RATES

6.4

6.2

7.2

7.0

MAX

220-

05

LOAD CAPACITANCE (pF)

V OH

(V)

15001000500 2000

6.8

6.6

160kbits/sec80kbits/sec20kbits/sec

TA = +25°CVCC = +5V3 TRANSMITTERS LOADEDRL = 3kΩC1–C4 = 1µF

12.0

4.00 2500

TRANSMITTER SLEW RATEvs. LOAD CAPACITANCE

6.0

5.0

11.0

9.0

10.0

MAX

220-

06


SLEW

RAT

E (V

/µs)

15001000500 2000

8.0

7.0

TA = +25°CVCC = +5VLOADED, RL = 3kΩC1–C4 = 1µF

1 TRANSMITTER LOADED

2 TRANSMITTERS LOADED



-6.0

-9.04.5 5.5

TRANSMITTER OUTPUTVOLTAGE (VOL) vs. VCC

-8.0

-8.5

-6.5

-7.0

MAX

220-

07

VCC (V)

V OL (

V)

5.0

-7.5


TA = +25°CC1–C4 = 1µFTRANSMITTERLOADS =3kΩ || 2500pF

1 TRANS-MITTERLOADED



-6.0

-7.60 2500

TRANSMITTER OUTPUT VOLTAGE (VOL) vs. LOAD CAPACITANCE AT


-7.0

-7.2

-7.4

-6.2

-6.4

MAX

220-

08


V OL (

V)

15001000500 2000

-6.6

-6.8 160kbits/sec80kbits/sec20Kkbits/sec

TA = +25°CVCC = +5V3 TRANSMITTERS LOADEDRL = 3kΩC1–C4 = 1µF

10

-100 5 10 15 20 25 30 35 40 45 50

TRANSMITTER OUTPUT VOLTAGE (V+, V-)vs. LOAD CURRENT

-2

-6

-4

-8

8

6

MAX

220-

09CURRENT (mA)

V+, V

- (V)

4

2

0V+ AND V-EQUALLYLOADED

V- LOADED,NO LOADON V+

TA = +25°CVCC = +5VC1–C4 = 1µF

ALL TRANSMITTERS UNLOADED

V+ LOADED,NO LOADON V-

__________________________________________Typical Operating CharacteristicsMAX223/MAX230–MAX241

*SHUTDOWN POLARITY IS REVERSED FOR NON MAX241 PARTS

V+, V- WHEN EXITING SHUTDOWN(1µF CAPACITORS)

MAX220-13

SHDN*

V-

O

V+

500ms/div

Input Logic Threshold Low

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8 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS—MAX225/MAX244–MAX249

ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless oth-erwise noted.)

Note 4: Input voltage measured with transmitter output in a high-impedance state, shutdown, or VCC = 0V.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage (VCC) ...............................................-0.3V to +6VInput VoltagesTIN‚ ENA, ENB, ENR, ENT, ENRA,ENRB, ENTA, ENTB..................................-0.3V to (VCC + 0.3V)RIN .....................................................................................±25VTOUT (Note 3).....................................................................±15VROUT ........................................................-0.3V to (VCC + 0.3V)

Short Circuit (one output at a time)TOUT to GND............................................................ContinuousROUT to GND............................................................Continuous

Continuous Power Dissipation (TA = +70°C)28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W40-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ...611mW44-Pin PLCC (derate 13.33mW/°C above +70°C) ...........1.07W

Operating Temperature RangesMAX225C_ _, MAX24_C_ _ ..................................0°C to +70°CMAX225E_ _, MAX24_E_ _ ...............................-40°C to +85°C

Storage Temperature Range .............................-65°C to +160°CLead Temperature (soldering,10sec) ..............................+300°C

VCC = 0V, VOUT = ±15V

µATables 1a–1d

±0.01 ±25

Normal operation

Shutdown

Tables 1a–1d, normal operation

All transmitter outputs loaded with 3kΩ to GND

ENA, ENB, ENT, ENTA, ENTB =VCC, VOUT = ±15V

VRS-232 Input Hysteresis

RS-232 Input Threshold Low V

V±5 ±7.5Output Voltage Swing

Output Leakage Current (shutdown)

±0.01 ±25

Ω300 10MVCC = V+ = V- = 0V, VOUT = ±2V (Note 4)Transmitter Output Resistance

µA

PARAMETER

±0.05 ±0.10

MIN TYP MAX UNITS

Normal operation, outputs disabled,Tables 1a–1d, 0V ≤ VOUT ≤ VCC, ENR_ = VCC

TTL/CMOS Output Leakage Current

10 30Shrinking VOUT = VCCmA

-2 -10Sourcing VOUT = GND

V3.5 VCC - 0.2IOUT = -1.0mATTL/CMOS Output Voltage High

V0.2 0.4IOUT = 3.2mATTL/CMOS Output Voltage Low

kΩ3 5 7

0.2 0.5 1.0VCC = 5V

1.4 0.8 V

TTL/CMOS Output Short-Circuit Current

V1.8 2.4

0.8 1.3VCC = 5V

RS-232 Input Resistance

V±25RS-232 Input Voltage Operating Range

mA±7 ±30VOUT = 0VOutput Short-Circuit Current

kbits/sec120 64Data Rate

CONDITIONS

VCC = 5V

µA±0.01 ±1

Logic Pull-Up/lnput Current10 50

Tables 1a–1d

RS-232 Input Threshold High

V2 1.4Input Logic Threshold High

RS-232 TRANSMITTERS

RS-232 RECEIVERS

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_______________________________________________________________________________________ 9

Operating Supply Voltage4.75 5.25

V

Transmitter Enable Time

MAX225 10 20

tET

No loadMAX244–MAX249 11 30

5 10 30

MAX225 40VCC Supply Current (normal operation) 3kΩ loads on

all outputs MAX244–MAX249 57

mA

Transition Slew Rate

8 25

CL = 50pF to 2500pF, RL = 3kΩ to 7kΩ, VCC = 5V, TA = +25°C, measured from +3V to -3V or -3V to +3V

TA = TMIN to TMAX

CONDITIONS

50

V/µs

MAX246–MAX249 (excludes charge-pump start-up)

Shutdown Supply Current µA

5

tPHLT 1.3 3.5

µs

tPLHT 1.5 3.5

Transmitter Disable Time, Figure 4

Transmitter Propagation DelayTLL to RS-232 (normal operation), Figure 1

µs

tDT 100 ns

Transmitter + to - Propagation Delay Difference (normal operation)

tPHLT - tPLHT

UNITSMIN TYP MAX

350

PARAMETER

ns

Receiver + to - Propagation Delay Difference (normal operation)

tPHLR - tPLHR 350 ns

4.5 5.5MAX244–MAX249

MAX225

Leakage current ±1

Threshold low 1.4 0.8Control Input

Threshold high 2.4 1.4V

µA

TA = +25°C

tPHLR 0.6 1.5

tPLHR 0.6 1.5

Receiver Propagation DelayTLL to RS-232 (normal operation),Figure 2

µs

tPHLS 0.6 10

tPLHS 3.0 10

Receiver Propagation Delay TLL to RS-232 (low-power mode), Figure 2

µs

Receiver-Output Enable Time, Figure 3 tER 100 500 ns

Receiver-Output Disable Time, Figure 3 tDR 100 500 ns

MAX225/MAX245–MAX249(includes charge-pump start-up)

10 ms

POWER SUPPLY AND CONTROL LOGIC

AC CHARACTERISTICS

Note 5: The 300Ω minimum specification complies with EIA/TIA-232E, but the actual resistance when in shutdown mode or VCC =0V is 10MΩ as is implied by the leakage specification.

ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249 (continued)(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless oth-erwise noted.)

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10 ______________________________________________________________________________________

__________________________________________Typical Operating Characteristics

MAX225/MAX244–MAX249

18

20 1 2 3 4 5

TRANSMITTER SLEW RATEvs. LOAD CAPACITANCE

8

6

4

16 MAX

220-

10

LOAD CAPACITANCE (nF)

TRAN

SMIT

TER

SLEW

RAT

E (V

/µs)

14

12

10

VCC = 5V

EXTERNAL POWER SUPPLY1µF CAPACITORS

40kb/s DATA RATE 8 TRANSMITTERSLOADED WITH 3kΩ

10

-100 5 10 15 20 25 30 35

OUTPUT VOLTAGEvs. LOAD CURRENT FOR V+ AND V-

-2

-4

-6

-8

8

MAX

220-

11

LOAD CURRENT (mA)

OUTP

UT V

OLTA

GE (V

)

6

4

2

0

V+ AND V- LOADEDEITHER V+ OR V- LOADED

V+ AND V- LOADED

VCC = 5VEXTERNAL CHARGE PUMP1µF CAPACITORS 8 TRANSMITTERSDRIVING 5kΩ AND2000pF AT 20kbits/sec

V- LOADED

V+ LOADED

9.0

5.00 1 2 3 4 5

TRANSMITTER OUTPUT VOLTAGE (V+, V-)vs. LOAD CAPACITANCE AT


6.0

5.5

8.5 MAX

220-

12

LOAD CAPACITANCE (nF)

V+, V

(V)

8.0

7.5

7.0

6.5

VCC = 5V WITH ALL TRANSMITTERS DRIVENLOADED WITH 5kΩ

10kb/sec

20kb/sec

40kb/sec

60kb/sec

100kb/sec200kb/sec

ALL CAPACITIORS 1µF

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______________________________________________________________________________________ 11

INPUT

OUTPUT

+3V

V+

0VV-

0V

tPLHT tPHLT

tPHLRtPHLS

tPLHRtPLHS

50%VCC

50%+3V

50%INPUT

OUTPUT

*EXCEPT FOR R2 ON THE MAX243 WHERE -3V IS USED.

0V*

50%GND

Figure 1. Transmitter Propagation-Delay Timing Figure 2. Receiver Propagation-Delay Timing

EN

RX IN

a) TEST CIRCUIT

b) ENABLE TIMING

c) DISABLE TIMING

EN INPUT

RECEIVEROUTPUTS

RX OUTRX

1k

0V

+3V

EN

EN

+0.8V

+3.5V

OUTPUT ENABLE TIME (tER)

VCC - 2V

VOL + 0.5V

VOH - 0.5V

OUTPUT DISABLE TIME (tDR)

VCC - 2V

+3V

0V

150pF

EN INPUT

VOH

RECEIVEROUTPUTS

VOL

1 OR 0 TX

3k 50pF

-5V

+5V

OUTPUT DISABLE TIME (tDT)V+

SHDN+3V

0V

V-

0V

a) TIMING DIAGRAM

b) TEST CIRCUIT

Figure 3. Receiver-Output Enable and Disable Timing Figure 4. Transmitter-Output Disable Timing

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12 ______________________________________________________________________________________

ENT ENR OPERATION STATUS TRANSMITTERS RECEIVERS

0 0 Normal Operation All Active All Active

0 1 Normal Operation All Active All 3-State

1 0 Shutdown All 3-State All Low-Power Receive Mode

1 1 Shutdown All 3-State All 3-State

Table 1a. MAX245 Control Pin Configurations

ENT ENROPERATION

STATUSTRANSMITTERS RECEIVERS

TA1–TA4 TB1–TB4 RA1–RA5 RB1–RB5

0 0 Normal Operation All Active All Active All Active All Active

0 1 Normal Operation All Active All ActiveRA1–RA4 3-State,RA5 Active

RB1–RB4 3-State,RB5 Active

1 0 Shutdown All 3-State All 3-StateAll Low-PowerReceive Mode

All Low-PowerReceive Mode

1 1 Shutdown All 3-State All 3-StateRA1–RA4 3-State,RA5 Low-PowerReceive Mode

RB1–RB4 3-State,RB5 Low-PowerReceive Mode

Table 1b. MAX245 Control Pin Configurations

Table 1c. MAX246 Control Pin Configurations

ENA ENBOPERATION

STATUSTRANSMITTERS RECEIVERS


0 0 Normal Operation All Active All Active All Active All Active

0 1 Normal Operation All Active All 3-State All ActiveRB1–RB4 3-State,RB5 Active

1 0 Shutdown All 3-State All ActiveRA1–RA4 3-State,RA5 Active

All Active

1 1 Shutdown All 3-State All 3-StateRA1–RA4 3-State,RA5 Low-PowerReceive Mode

RB1–RB4 3-State,RA5 Low-PowerReceive Mode

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______________________________________________________________________________________ 13


0 0 0 0 Normal Operation All Active All Active All Active All Active

0 0 0 1 Normal Operation All Active All Active All ActiveAll 3-State, exceptRB5 stays active onMAX247

0 0 1 0 Normal Operation All Active All Active All 3-State All Active

0 0 1 1 Normal Operation All Active All Active All 3-StateAll 3-State, exceptRB5 stays active onMAX247

0 1 0 0 Normal Operation All Active All 3-State All Active All Active

0 1 0 1 Normal Operation All Active All 3-State All ActiveAll 3-State, exceptRB5 stays active onMAX247

0 1 1 0 Normal Operation All Active All 3-State All 3-State All Active

0 1 1 1 Normal Operation All Active All 3-State All 3-StateAll 3-State, exceptRB5 stays active onMAX247

1 0 0 0 Normal Operation All 3-State All Active All Active All Active

1 0 0 1 Normal Operation All 3-State All Active All ActiveAll 3-State, exceptRB5 stays active onMAX247

1 0 1 0 Normal Operation All 3-State All Active All 3-State All Active

1 0 1 1 Normal Operation All 3-State All Active All 3-StateAll 3-State, exceptRB5 stays active onMAX247

1 1 0 0 Shutdown All 3-State All 3-StateLow-PowerReceive Mode

Low-PowerReceive Mode

1 1 0 1 Shutdown All 3-State All 3-StateLow-PowerReceive Mode

All 3-State, exceptRB5 stays active onMAX247

1 1 1 0 Shutdown All 3-State All 3-State All 3-StateLow-PowerReceive Mode

1 1 1 1 Shutdown All 3-State All 3-State All 3-StateAll 3-State, exceptRB5 stays active onMAX247

Table 1d. MAX247/MAX248/MAX249 Control Pin Configurations

MAX248OPERATION

STATUSENRBMAX247 TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB5

TRANSMITTERS

ENRAENTBENTA

MAX249 TA1–TA3 TB1–TB3 RA1–RA5 RB1–RB5

RECEIVERS

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49 _______________Detailed Description

The MAX220–MAX249 contain four sections: dualcharge-pump DC-DC voltage converters, RS-232 dri-vers, RS-232 receivers, and receiver and transmitterenable control inputs.

Dual Charge-Pump Voltage ConverterThe MAX220–MAX249 have two internal charge-pumpsthat convert +5V to ±10V (unloaded) for RS-232 driveroperation. The first converter uses capacitor C1 to dou-ble the +5V input to +10V on C3 at the V+ output. Thesecond converter uses capacitor C2 to invert +10V to -10V on C4 at the V- output.

A small amount of power may be drawn from the +10V(V+) and -10V (V-) outputs to power external circuitry(see the Typical Operating Characteristics section),except on the MAX225 and MAX245–MAX247, wherethese pins are not available. V+ and V- are not regulated,so the output voltage drops with increasing load current.Do not load V+ and V- to a point that violates the mini-mum ±5V EIA/TIA-232E driver output voltage whensourcing current from V+ and V- to external circuitry.

When using the shutdown feature in the MAX222,MAX225, MAX230, MAX235, MAX236, MAX240,MAX241, and MAX245–MAX249, avoid using V+ and V-to power external circuitry. When these parts are shutdown, V- falls to 0V, and V+ falls to +5V. For applica-tions where a +10V external supply is applied to the V+pin (instead of using the internal charge pump to gen-erate +10V), the C1 capacitor must not be installed andthe SHDN pin must be tied to VCC. This is because V+is internally connected to VCC in shutdown mode.

RS-232 DriversThe typical driver output voltage swing is ±8V whenloaded with a nominal 5kΩ RS-232 receiver and VCC =+5V. Output swing is guaranteed to meet the EIA/TIA-232E and V.28 specification, which calls for ±5V mini-mum driver output levels under worst-case conditions.These include a minimum 3kΩ load, VCC = +4.5V, andmaximum operating temperature. Unloaded driver out-put voltage ranges from (V+ -1.3V) to (V- +0.5V).

Input thresholds are both TTL and CMOS compatible.The inputs of unused drivers can be left unconnectedsince 400kΩ input pull-up resistors to VCC are built in(except for the MAX220). The pull-up resistors force theoutputs of unused drivers low because all drivers invert.The internal input pull-up resistors typically source 12µA,except in shutdown mode where the pull-ups are dis-abled. Driver outputs turn off and enter a high-imped-ance state—where leakage current is typicallymicroamperes (maximum 25µA)—when in shutdown

mode, in three-state mode, or when device power isremoved. Outputs can be driven to ±15V. The power-supply current typically drops to 8µA in shutdown mode.The MAX220 does not have pull-up resistors to force theoutputs of the unused drivers low. Connect unusedinputs to GND or VCC.

The MAX239 has a receiver three-state control line, andthe MAX223, MAX225, MAX235, MAX236, MAX240,and MAX241 have both a receiver three-state controlline and a low-power shutdown control. Table 2 showsthe effects of the shutdown control and receiver three-state control on the receiver outputs.

The receiver TTL/CMOS outputs are in a high-imped-ance, three-state mode whenever the three-state enableline is high (for the MAX225/MAX235/MAX236/MAX239–MAX241), and are also high-impedance whenever theshutdown control line is high.

When in low-power shutdown mode, the driver outputsare turned off and their leakage current is less than 1µAwith the driver output pulled to ground. The driver outputleakage remains less than 1µA, even if the transmitteroutput is backdriven between 0V and (VCC + 6V). Below-0.5V, the transmitter is diode clamped to ground with1kΩ series impedance. The transmitter is also zenerclamped to approximately VCC + 6V, with a seriesimpedance of 1kΩ.

The driver output slew rate is limited to less than 30V/µsas required by the EIA/TIA-232E and V.28 specifica-tions. Typical slew rates are 24V/µs unloaded and10V/µs loaded with 3Ω and 2500pF.

RS-232 ReceiversEIA/TIA-232E and V.28 specifications define a voltagelevel greater than 3V as a logic 0, so all receivers invert.Input thresholds are set at 0.8V and 2.4V, so receiversrespond to TTL level inputs as well as EIA/TIA-232E andV.28 levels.

The receiver inputs withstand an input overvoltage upto ±25V and provide input terminating resistors with


14 ______________________________________________________________________________________

PART SHDN EN EN(R) RECEIVERS

MAX223 __LowHighHigh

XLowHigh

High ImpedanceActiveHigh Impedance

MAX225 __ __High ImpedanceActive

__

MAX235MAX236MAX240

LowLowHigh

__ __LowHighX

High ImpedanceActiveHigh Impedance

Table 2. Three-State Control of Receivers

LowHigh

SHDN

__

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______________________________________________________________________________________ 15

nominal 5kΩ values. The receivers implement Type 1interpretation of the fault conditions of V.28 andEIA/TIA-232E.

The receiver input hysteresis is typically 0.5V with aguaranteed minimum of 0.2V. This produces clear out-put transitions with slow-moving input signals, evenwith moderate amounts of noise and ringing. Thereceiver propagation delay is typically 600ns and isindependent of input swing direction.

Low-Power Receive ModeThe low-power receive-mode feature of the MAX223,MAX242, and MAX245–MAX249 puts the IC into shut-down mode but still allows it to receive information. Thisis important for applications where systems are periodi-cally awakened to look for activity. Using low-powerreceive mode, the system can still receive a signal thatwill activate it on command and prepare it for communi-cation at faster data rates. This operation conservessystem power.

Negative Threshold—MAX243The MAX243 is pin compatible with the MAX232A, differ-ing only in that RS-232 cable fault protection is removedon one of the two receiver inputs. This means that controllines such as CTS and RTS can either be driven or leftfloating without interrupting communication. Differentcables are not needed to interface with different pieces ofequipment.

The input threshold of the receiver without cable faultprotection is -0.8V rather than +1.4V. Its output goespositive only if the input is connected to a control linethat is actively driven negative. If not driven, it defaultsto the 0 or “OK to send” state. Normally‚ the MAX243’sother receiver (+1.4V threshold) is used for the data line(TD or RD)‚ while the negative threshold receiver is con-nected to the control line (DTR‚ DTS‚ CTS‚ RTS, etc.).

Other members of the RS-232 family implement theoptional cable fault protection as specified by EIA/TIA-232E specifications. This means a receiver output goeshigh whenever its input is driven negative‚ left floating‚or shorted to ground. The high output tells the serialcommunications IC to stop sending data. To avoid this‚the control lines must either be driven or connectedwith jumpers to an appropriate positive voltage level.

Shutdown—MAX222–MAX242 On the MAX222‚ MAX235‚ MAX236‚ MAX240‚ andMAX241‚ all receivers are disabled during shutdown.On the MAX223 and MAX242‚ two receivers continue tooperate in a reduced power mode when the chip is inshutdown. Under these conditions‚ the propagationdelay increases to about 2.5µs for a high-to-low inputtransition. When in shutdown, the receiver acts as aCMOS inverter with no hysteresis. The MAX223 andMAX242 also have a receiver output enable input (ENfor the MAX242 and EN for the MAX223) that allowsreceiver output control independent of SHDN (SHDNfor MAX241). With all other devices‚ SHDN (SHDN forMAX241) also disables the receiver outputs.

The MAX225 provides five transmitters and fivereceivers‚ while the MAX245 provides ten receivers andeight transmitters. Both devices have separate receiverand transmitter-enable controls. The charge pumpsturn off and the devices shut down when a logic high isapplied to the ENT input. In this state, the supply cur-rent drops to less than 25µA and the receivers continueto operate in a low-power receive mode. Driver outputsenter a high-impedance state (three-state mode). Onthe MAX225‚ all five receivers are controlled by theENR input. On the MAX245‚ eight of the receiver out-puts are controlled by the ENR input‚ while the remain-ing two receivers (RA5 and RB5) are always active.RA1–RA4 and RB1–RB4 are put in a three-state modewhen ENR is a logic high.

Receiver and Transmitter Enable Control Inputs

The MAX225 and MAX245–MAX249 feature transmitterand receiver enable controls.

The receivers have three modes of operation: full-speedreceive (normal active)‚ three-state (disabled)‚ and low-power receive (enabled receivers continue to functionat lower data rates). The receiver enable inputs controlthe full-speed receive and three-state modes. Thetransmitters have two modes of operation: full-speedtransmit (normal active) and three-state (disabled). Thetransmitter enable inputs also control the shutdownmode. The device enters shutdown mode when alltransmitters are disabled. Enabled receivers function inthe low-power receive mode when in shutdown.

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has no control pins and is not included in these tables.

The MAX246 has ten receivers and eight drivers withtwo control pins, each controlling one side of thedevice. A logic high at the A-side control input (ENA)causes the four A-side receivers and drivers to go intoa three-state mode. Similarly, the B-side control input(ENB) causes the four B-side drivers and receivers togo into a three-state mode. As in the MAX245, one A-side and one B-side receiver (RA5 and RB5) remainactive at all times. The entire device is put into shut-down mode when both the A and B sides are disabled(ENA = ENB = +5V).

The MAX247 provides nine receivers and eight driverswith four control pins. The ENRA and ENRB receiverenable inputs each control four receiver outputs. TheENTA and ENTB transmitter enable inputs each controlfour drivers. The ninth receiver (RB5) is always active.The device enters shutdown mode with a logic high onboth ENTA and ENTB.

The MAX248 provides eight receivers and eight driverswith four control pins. The ENRA and ENRB receiverenable inputs each control four receiver outputs. TheENTA and ENTB transmitter enable inputs control fourdrivers each. This part does not have an always-activereceiver. The device enters shutdown mode and trans-mitters go into a three-state mode with a logic high onboth ENTA and ENTB.

The MAX249 provides ten receivers and six drivers withfour control pins. The ENRA and ENRB receiver enableinputs each control five receiver outputs. The ENTAand ENTB transmitter enable inputs control three dri-vers each. There is no always-active receiver. Thedevice enters shutdown mode and transmitters go intoa three-state mode with a logic high on both ENTA andENTB. In shutdown mode, active receivers operate in alow-power receive mode at data rates up to20kbits/sec.

__________Applications InformationFigures 5 through 25 show pin configurations and typi-cal operating circuits. In applications that are sensitiveto power-supply noise, VCC should be decoupled toground with a capacitor of the same value as C1 andC2 connected as close as possible to the device.


16 ______________________________________________________________________________________

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______________________________________________________________________________________ 17

TOP VIEW

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VCC

GND

T1OUT

R1INC2+

C1-

V+

C1+

MAX220MAX232

MAX232A R1OUT

T1IN

T2IN

R2OUTR2IN

T2OUT

V-

C2-

DIP/SO

V+

V-

2 +10VC1+C1

C2

1

34

5

11

10

12

9

6

14

7

13

8

T1IN

R1OUT

T2IN

R2OUT

T1OUT

R1IN

T2OUT

R2IN

+5V INPUT

C2+ -10V

C4

RS-232OUTPUTS

RS-232INPUTS

TTL/CMOSINPUTS

TTL/CMOSOUTPUTS

GND15

5k

5k

400k

400k+5V

+5V

+10V TO -10VVOLTAGE INVERTER

+5V TO +10VVOLTAGE DOUBLER

16

C3

C5

CAPACITANCE (µF)DEVICEMAX220MAX232MAX232A

C14.71.00.1

C24.71.00.1

C3101.00.1

C4101.00.1

C54.71.00.1

C2-

C1-

VCC

5k

DIP/SO

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

SHDN

VCC

GND

T1OUTC1-

V+

C1+

(N.C.) EN

R1IN

R1OUT

T1IN

T2INT2OUT

V-

C2-

C2+

109 R2OUTR2IN

MAX222MAX242

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

SHDN

VCC

GND

T1OUTC1-

V+

C1+

(N.C.) EN

N.C.

R1IN

R1OUT

N.C.T2OUT

V-

C2-

C2+

12

11

9

10

T1IN

T2INR2OUT

R2IN

MAX222MAX242

SSOP

( ) ARE FOR MAX222 ONLY.PIN NUMBERS IN TYPICAL OPERATING CIRCUIT ARE FOR DIP/SO PACKAGES ONLY.

V+

V-

3 +10VC1

C2

2

45

6

12

11

13

7

15

8

14

9

T1IN

R1OUT

T2IN

R2OUT

T1OUT

(EXCEPT MAX220)

(EXCEPT MAX220)

R1IN

T2OUT

R2IN

+5V INPUT

C2+ -10V

C4

RS-232OUTPUTS

RS-232INPUTS

TTL/CMOSINPUTS

TTL/CMOSOUTPUTS

GND16

5k

400k

400k+5V

+5V


VCC+5V TO +10V

VOLTAGE DOUBLER

17

C3

C5

1

10

18SHDN

EN(N.C.)

ALL CAPACITORS = 0.1µF

C2-

C1+C1-

TOP VIEW

Figure 5. MAX220/MAX232/MAX232A Pin Configuration and Typical Operating Circuit

Figure 6. MAX222/MAX242 Pin Configurations and Typical Operating Circuit

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18 ______________________________________________________________________________________

13

14

28

27

26

25

24

23

22

21

1

2

3

4

5

6

7

8

VCC

VCC VCC

400k

400k

400k

400k

400k

T1OUT+5V

+5V

0.1

+5V

3

28 27

4

25

24

23

26

5

6

7

22

GNDENRENR

GND

21

+5V

+5V

+5V

T2OUT

T3OUT

T4OUT

5k

5k

5k

5k

5k

1413

21

T5OUT

T5OUT

R1IN

R2IN

R3IN

R4IN

R5IN

T1IN11

12

18

17

16

15

10

9

8

19

20

T2IN

T3IN

T4IN

T5IN

ENT

R2OUT

R3OUT

R4OUT

PINS (ENR, GND, VCC, T5OUT) ARE INTERNALLY CONNECTED.CONNECT EITHER OR BOTH EXTERNALLY. T5OUT IS A SINGLE DRIVER.

R5OUT

R1OUT

VCC

ENT

T3INT2IN

T1IN

ENR

ENR

T4IN

T5IN

R4OUT

R5OUTR3IN

R3OUT

R2OUT

R1OUT

20

19

18

17

9

10

11

12

R5IN

R4IN

T3OUT

T4OUTT2OUT

T1OUT

R1IN

R2IN

SO

MAX225

16

15

T5OUT

MAX225 FUNCTIONAL DESCRIPTION5 RECEIVERS5 TRANSMITTERS2 CONTROL PINS 1 RECEIVER ENABLE (ENR) 1 TRANSMITTER ENABLE (ENT)

T5OUTGND

GND

TOP VIEW

Figure 7. MAX225 Pin Configuration and Typical Operating Circuit

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______________________________________________________________________________________ 19

GND

10

27R3OUT

23R4OUT

R3IN

R4IN

5k

5k

5 4R2OUT R2IN

5k

RS-232INPUTS

LOGICOUTPUTS

RS-232OUTPUTS

TTL/CMOSINPUTS

R2

8 9R1OUT R1IN

5k

R1

R3

R4

19 18R5OUT R5IN

5kR5

27 T1IN T1OUT

+5V400k

+5V

6 3T2IN T2OUTT2

400k

20 T3OUT 1T3IN

+5V

T3

400k

C1+

C1-

1.0µF

12VCC

+5V INPUT

11

17

1.0µF

131.0µF


26

1.0µF

T1

2821 T4IN T4OUT

+5V400k

T4

14

C2+

C2-

15

1.0µF 16+10V TO -10V

VOLTAGE INVERTER

V+

22

EN (EN)24 25

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

T4OUT

R3IN

R3OUT

SHDN (SHDN)

R4IN*

C2+

R4OUT*

T4IN

T3IN

R5OUT*

R5IN*

V-

C2-

C1-

V+

C1+

VCC

GND

R1IN

R1OUT

T1IN

T2IN

R2OUT

R2IN

T2OUT

T1OUT

T3OUT

Wide SO/SSOP

MAX223MAX241

EN (EN)

SHDN(SHDN)

*R4 AND R5 IN MAX223 REMAIN ACTIVE IN SHUTDOWN

NOTE: PIN LABELS IN ( ) ARE FOR MAX241

V-

TOP VIEW

Figure 8. MAX223/MAX241 Pin Configuration and Typical Operating Circuit

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20 ______________________________________________________________________________________

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

T5IN

N.C.

SHDNT2IN

T2OUT

T1OUT

T5OUT

T4IN

T3IN

V-C1+

VCC

GND

T1IN

12

11

9

10

C2-

C2+C1-

V+

DIP/SO

MAX230

V+

V-

9C1+C1-

810

1112

5

4

14

13

2

3

1

20

T3IN

T4IN

T2IN

T5IN

T1OUT

T2OUT

+5V INPUT

C2+C2-

RS-232OUTPUTS

TTL/CMOSINPUTS

GND6

400k+5V

400k+5V

400k+5V

400k+5V

400k+5V


VCC+5V TO +10V

VOLTAGE DOUBLER

7

1.0µF

1.0µF

1.0µF

1.0µF

19

15

16

T3OUT T4OUT

18x

T1IN

T3OUT

T4OUT

T5OUT

17

1.0µF

T2

T3

T4

T5

N.C. SHDN

T1

TOP VIEW


V+

V-

14C1+

C1-

1

2

8

7

3

11

4T2IN

T1IN T1OUT

T2OUT

+5V INPUT

RS-232INPUTS

TTL/CMOSOUTPUTS

GND

12 (14)

5k

5k

+12V TO -12VVOLTAGE CONVERTER

13 (15)

1.0µF

1.0µFC2

1.0µF

400k

+5V

400k

+5V

6

9 10R1IN

R2INR2OUT

R1OUT

5

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

V+

VCC

GND

T1OUTT2OUT

V-

C-

C+

MAX231

R1IN

R1OUT

T1IN

N.C.N.C.

T2IN

R2OUT

R2IN

SO

(12)

RS-232OUTPUTS

TTL/CMOSINPUTS

(11)

(13)(10)

VCC

PIN NUMBERS IN ( ) ARE FOR SO PACKAGE

14

13

12

11

10

9

8

1

2

3

4

5

6

7

V+

VCC

GND

T1OUTT2OUT

V-

C-

C+

MAX231

R1IN

R1OUT

T1INT2IN

R2OUT

R2IN

DIP

+7.5V TO +12V

(16)

T1

T2

R1

R2

TOP VIEW

Figure 10. MAX231 Pin Configurations and Typical Operating Circuit

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______________________________________________________________________________________ 21

2

1

5

18T2IN

T1IN T1OUT

T2OUT

+5V INPUT

RS-232OUTPUTS

TTL/CMOSOUTPUTS

GND GND6 9

400k

+5V

400k

+5V

5k

5k

7

20

3 4R1IN

R2INR2OUT

R1OUT

19

RS-232OUTPUTS

TTL/CMOSINPUTS

VCC

( ) ARE FOR SO PACKAGE ONLY.

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

R2IN

T2OUT

V-R1IN

R1OUT

T1IN

C2-

C2+

V+ (C1-)

C1- (C1+)(V+) C1+

VCC

GND

T1OUT

12

11

9

10

V- (C2+)

C2+ (C2-)(V-) CS-

GND

DIP/SO

MAX233MAX233A

T2IN R2OUT

C1+

C1-

V-

V-

V+

C2+

C2-

C2-

C2+

8 (13)

13 (14)

12 (10)

17

14 (8)

11 (12)

15

16

10 (11)

DO NOT MAKECONNECTIONS TO

THESE PINS

INTERNAL -10POWER SUPPLY

INTERNAL +10VPOWER SUPPLY

1.0µFTOP VIEW

Figure 11. MAX233/MAX233A Pin Configuration and Typical Operating Circuit

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

T3OUT

T4OUT

T4IN

T3INT1IN

T2IN

T2OUT

T1OUT

MAX234

V-

C2-

C2+

C1-V+

C1+

VCC

GND

DIP/SO

V+

V-

8C1+

C1-

1.0µF

1.0µF

1.0µF

7

9

10

11

4

3

13

14

12

1

3

16

15

T1IN

T3IN

T2IN

T4IN

T1OUT

T3OUT

T2OUT

T4OUT

+5V INPUT

C2-

C2+

RS-232OUTPUTS

TTL/CMOSINPUTS

GND5

+5V

+5V


VCC+5V TO +10V

VOLTAGE DOUBLER

6

+5V

+5V

400k

400k

400k

400k

1.0µF

1.0µF

T1

T2

T4

T3

TOP VIEW


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22 ______________________________________________________________________________________

1.0µF+5V INPUT

GND

11

6

23

5R2OUT

RS-232INPUTS

TTL/CMOSOUTPUTS

14 13

21

R5OUT

5k

17 18R4OUT

5k

24R3OUT

5k

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

R3IN

R3OUT

T5IN

SHDNT2OUT

T1OUT

T3OUT

T4OUT

EN

T5OUT

R4IN

R4OUTT1IN

T2IN

R2OUT

R2IN

16

15

14

13

9

10

11

12

T4IN

T3IN

R5OUT

R5INVCC

GND

R1IN

R1OUT

DIP

MAX235

5k

9 10R1OUT R1IN

R2IN

R3IN

R4IN

R5IN

5k

7

15

3

4T2IN

T3OUT RS-232OUTPUTS

TTL/CMOSINPUTS

22 19T5IN T5OUT

+5V

16 1T4IN T4OUT

+5V

2T3IN

+5V

+5V

8 T1IN T1OUT

+5V

T2OUT

T1

T1

R2

R3

R4

R5

T2

T3

T5

T4

400k

400k

400k

400k

400k

SHDNEN20

12

VCC

TOP VIEW


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______________________________________________________________________________________ 23

GND

8

23R2OUT RS-232INPUTS

TTL/CMOSOUTPUTS

17 16

21

R3OUT

R2IN

R3IN

5k

5k

5 4R1OUT R1IN

5k

RS-232OUTPUTS

TTL/CMOSINPUTS

R1

R2

R3

27 T1IN T1OUT

+5V

T1

400k

6 3T2IN

+5V

T2OUTT2

400k

18 T3OUT 1T3IN

+5V

T3

400k

19 24T4IN T4OUT

+5V

T4

400k

SHDNEN20

11C1+

C1-

1.0µF

10

12

13

14

15

+5V INPUT

C2+

C2-

VCC+5V TO +10V

VOLTAGE DOUBLER

9 1.0µF

1.0µF+10V TO -10VVOLTAGE INVERTER

22

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

T4OUT

R2IN

R2OUT

SHDNR1IN

T2OUT

T1OUT

T3OUT

T4IN

T3IN

R3OUTGND

T1IN

T2IN

R1OUT

16

15

14

13

9

10

11

12

R3IN

V-

C2-

C2+C1-

V+

C1+

VCC

DIP/SO

MAX236 EN

1.0µF

1.0µF

TOP VIEW

V+

V-


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20

–MA

X2

49


24 ______________________________________________________________________________________

GND

8

23R2OUT RS-232INPUTS

TTL/CMOSOUTPUTS

17 16R3OUT

R2IN

R3IN

5k

5k

5 4R1OUT R1IN

5k

RS-232OUTPUTS

TTL/CMOSINPUTS

R1

R2

R3

27 T1IN T1OUT

+5V

T1

400k

6 3T2IN

+5V

T2OUTT2

400k

18 T3OUT 1T3IN

+5V

T3

400k

21 20T5IN T5OUT

+5V

T5

400k

11C1+

C1-

1.0µF

10

12

13

14

15

+5V INPUT

C2+

C2-

VCC+5V TO +10V

VOLTAGE DOUBLER

9 1.0µF

1.0µF+10V TO -10V

VOLTAGE INVERTER

22

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

T4OUT

R2IN

R2OUT

T5INR1IN

T2OUT

T1OUT

T3OUT

T4IN

T3IN

R3OUTGND

T1IN

T2IN

R1OUT

16

15

14

13

9

10

11

12

R3IN

V-

C2-

C2+C1-

V+

C1+

VCC

DIP/SO

MAX237 T5OUT

1.0µF

1.0µF

19 24T4IN T4OUT

+5V

T4

400k

V+

V-

TOP VIEW


MA

X2

20

–MA

X2

49


______________________________________________________________________________________ 25

GND

8

3R2OUT

22 23R3OUT

R2IN

R3IN

5k

5k

6 7R1OUT R1IN

5k

RS-232OUTPUTS

TTL/CMOSINPUTS

RS-232INPUTS

TTL/CMOSOUTPUTS

R1

R2

R3

17 16R4OUT R4IN

5k

R4

25 T1IN T1OUT

+5V400k

+5V

18 1T2IN T2OUTT2

400k

19 T3OUT 24T3IN

+5V

T3

400k

11C1+

C1-

1.0µF

10

12

13

1415

+5V INPUT

C2+

C2-

VCC+5V TO +10V

VOLTAGE DOUBLER

9 1.0µF

1.0µF+10V TO -10V

VOLTAGE INVERTER

4

1.0µF

1.0µF

21 20T4IN T4OUT

+5V

T4

400k

T124

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

T3OUT

R3IN

R3OUT

T4INR2OUT

R2IN

T1OUT

T2OUT

TOP VIEW

T3IN

T2IN

R4OUTGND

R1IN

R1OUT

T1IN

16

15

14

13

9

10

11

12

R4IN

V-

C2-

C2+C1-

V+

C1+

VCC

DIP/SO

MAX238 T4OUT

V+

V-


MA

X2

20

–MA

X2

49


26 ______________________________________________________________________________________

GND

3

18R3OUT

12R4OUT

R3IN

R4IN

5k

5k

22 21R2OUT R2IN

5k

RS-232OUTPUTS

TTL/CMOSINPUTS

RS-232INPUTS

TTL/CMOSOUTPUTS

R2

1 2R1OUT R1IN

5k

R1

R3

R4

10 9R5OUT R5IN

5k

R5

1924 T1IN T1OUT

+5V400k

+5V

23 20T2IN T2OUTT2

400k

16 T3OUT 13T3IN

+5V

T3

400k

C1+

C1-

1.0µF

6 VCC 8

+5V INPUT

4 5

1.0µF+10V TO -10V

VOLTAGE INVERTER

17

1.0µF

T1

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

T1IN

T2IN

R2OUT

R2INVCC

GND

R1IN

R1OUT

T1OUT

R3IN

R3OUTV-

C-

C+

V+

16

15

14

13

9

10

11

12

T3IN

N.C.

EN

T3OUTR4IN

R4OUT

R5OUT

R5IN

DIP/SO

MAX239 T2OUT

7.5V TO 13.2VINPUT

7

V+

11

EN14 15N.C.

V-

TOP VIEW


MA

X2

20

–MA

X2

49


______________________________________________________________________________________ 27

GND

18

4R3OUT

40R4OUT

R3IN

R4IN

5k

5k

13 10R2OUT R2IN

5k

RS-232INPUTS

TTL/CMOSOUTPUTS

RS-232OUTPUTS

TTL/CMOSINPUTS

R2

16 17R1OUT R1IN

5kR1

R3

R4

36 35R5OUT R5IN

5k

R5

715 T1IN T1OUT

+5V 400k

+5V

14 8T2IN T2OUTT2

400k

37 T3OUT 6T3IN

+5V

T3

400k

C1+

C1-

1.0µF

25VCC

+5V INPUT

19

30

1.0µF

261.0µF


3

1.0µF

T1

+5V

2 41T5IN T5OUTT5

400k

538 T4IN T4OUT

+5V 400k

T4

27

C2+

C2-

28

1.0µF 29+5V TO -10V

VOLTAGE INVERTER

V+

39

EN42 43

Plastic FP

MAX240

SHDNENT5OUTR4INR4OUT

R5OUTR5INN.C.

N.C.

T3IN

T4IN

R2OUTT2INT1IN

R1OUTR1IN

N.C.N.C.N.C.

N.C.

VCC

GND

R2IN

N.C.

T4OU

T

T2OU

TT1

OUT

T3OU

T

N.C.

R3IN

R3OU

T

N.C.

T5IN

N.C.

C1+ C2V+ C1-

C2+

N.C. V-

N.C.

N.C.

N.C.

3332313029282726252423

3435363738394041424344

1234567891011

2221201918171615141312

SHDN

TOP VIEW

V-


MA

X2

20

–MA

X2

49


28 ______________________________________________________________________________________

V+

V-

2 +10VC1+

C1-

1

3

4

5

11

10

12

9

6

14

7

13

8

T1IN

R1OUT

T2IN

R2OUT

T1OUT

R1IN

T2OUT

R2IN

+5V INPUT

C2+

C2--10V

RS-232OUTPUTS

RS-232INPUTS

TTL/CMOSINPUTS

TTL/CMOSOUTPUTS

GND

15

5k

5k

400k

400k

+5V

+5V



16

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

C1+ VCC

GND

T1OUT

R1IN

R1OUT

T1IN

T2IN

R2OUT

MAX243

DIP/SO

V+

C1-

V-

C2+

C2-

T2OUT

R2IN

0.1µF

0.1µF

0.1µF

0.1µFALL CAPACITORS = 0.1µF

0.1µF

RECEIVER INPUT≤ -3 VOPEN≥ +3V

R1 OUTPUTHIGHHIGHLOW

R2 OUTPUTHIGHLOWLOW

TOP VIEW

VCC


MA

X2

20

–MA

X2

49


______________________________________________________________________________________ 29

400k

+10V TO -10V VOLTAGE INVERTER

+5V TO +10V VOLTAGE DOUBLERVCC

400k

400k

GND

+5V +5V

+5V +5V

+5V

25

2423

2120

2

1µF

1µF

1µF 1µF

1µF

16

3

17

4

18

5k

5k

5k

5k

5k

5k

5k

5k

5k

5k

C2-C2+

C1-C1+

TA2OUT

TA2IN

TA3OUT

TA3IN

TA4OUT

TA4IN

9 RA1IN

10 RA1OUT

8 RA2IN

11 RA2OUT

7 RA3IN

12 RA3OUT

6 RA4IN

13 RA4OUT

5 RA5IN

14

19

RA5OUT

26

22

43

29

42

28

41

27

36

35

37

34

38

33

39

32

40

31

V-

V+

TB2OUT

TB2IN

400k

2

15

TA1OUT

TA1IN

44

30

TB1OUT

TB1IN

TB3OUT

TB3IN

TB4OUT

TB4IN

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

RB5IN

RB5OUT

MAX249 FUNCTIONAL DESCRIPTION10 RECEIVERS 5 A-SIDE RECEIVER 5 B-SIDE RECEIVER8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERSNO CONTROL PINS

441234 404142435

21 24 2625 27 2822 2319 20

8

9

10

11

12

13

14

15

16

17 29

30

31

32

33

34

35

36

37

38

TA3IN

V CC

R A5IN

MAX244

PLCC

TOP VIEW

T A4O

UT

T A3O

UT

T A2O

UT

T A1O

UT

T B1O

UT

T B2O

UT

T B3O

UT

TB4O

UT

R B5IN

GND V+C1+

C2+

C1- V-C2-

T B3IN

T B4IN

RB3IN

RB2IN

RB1IN

RB1OUT

RB2OUT

RB3OUT

RB4OUT

RB5OUT

TB1IN

TB2IN

TA2IN

TA1IN

RA5OUT

RA4OUT

RA3OUT

RA2OUT

RA1OUT

RA1IN

RA2IN

7 39 RB4INRA3IN

6

18

R A4IN

T A4IN

+5V +5V

+5V +5V


MA

X2

20

–MA

X2

49


30 ______________________________________________________________________________________

400k

VCC

400k

400k

GND

+5V +5V

+5V +5V

+5V

40

17

1µF

3

18

4

19

5

5k

5k

5k

5k

5k

5k

5k

5k

5k

5k

TA2OUT

TA2IN

TA3OUT

TA3IN

TA4OUT

TA4IN

1

11 RA1IN

10 RA1OUT

12 RA2IN

9 RA2OUT

13 RA3IN

8 RA3OUT

14 RA4IN

7 RA4OUT

15 RA5IN

6

20

RA5OUT

23

37

22

36

21

35

29

30

28

31

27

32

26

33

25

34

TB2OUT

TB2IN

TB3OUT

TB3IN

TB4OUT

TB4IN

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

RB5IN

RB5OUT

+5V +5V

400k

16

2

TA1OUT

TA1IN

24

38

TB1OUT

TB1IN

+5V +5V40 VCC

ENT

TB1IN

TB2IN

TB3IN

TB4IN

RB5OUT

RB4OUT

RB3OUT

RB2OUT

RB1OUT

RB1IN

RB2IN

RB3IN

RB4IN

RB5IN

TB1OUT

TB2OUT

TB3OUT

TB4OUT

39

38

37

36

35

34

33

32

31

1

2

3

4

5

6

7

8

9

10

ENR

TA1IN

TA2IN

TA3IN

TA4IN

RA5OUT

RA4OUT

RA3OUT

RA2OUT

RA1OUT

RA1IN

RA2IN

RA3IN

RA4IN

RA5IN

TA1OUT

TA2OUT

TA3OUT

TA4OUT

GND

TOP VIEW

MAX245

30

29

28

27

26

25

24

23

22

21

11

12

13

14

15

16

17

18

19

DIP

20

MAX245 FUNCTIONAL DESCRIPTION10 RECEIVERS 5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE) 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)8 TRANSMITTTERS 4 A-SIDE TRANSMITTERS2 CONTROL PINS 1 RECEIVER ENABLE (ENR) 1 TRANSMITTER ENABLE (ENT)

39ENR ENT


MA

X2

20

–MA

X2

49


______________________________________________________________________________________ 31

400k

VCC

400k

GND

+5V

+5V

+5V

+5V

+5V

40

16

1µF

2

18

4

TA1OUT

TA1IN

TA3OUT

TA3IN

20

24

38

22

36

1 39

TB1OUT

TB1IN

TB3OUT

TB3IN

400k

+5V17

3

TA2OUT

TA2IN

+5V23

37

TB2OUT

TB2IN

400k

+5V19

5

TA4OUT

TA4IN

+5V21

35

TB4OUT

TB4IN

5k

5k

5k

5k

5k

5k

5k

5k

5k

5k

11 RA1IN

10 RA1OUT

12 RA2IN

9 RA2OUT

13 RA3IN

8 RA3OUT

14 RA4IN

7 RA4OUT

15 RA5IN

6 RA5OUT

29

30

28

31

27

32

26

33

25

34

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

RB5IN

RB5OUT

40 VCC

ENB

TB1IN

TB2IN

TB3IN

TB4IN

RB5OUT

RB4OUT

RB3OUT

RB2OUT

RB1OUT

RB1IN

RB2IN

RB3IN

RB4IN

RB5IN

TB1OUT

TB2OUT

TB3OUT

TB4OUT

39

38

37

36

35

34

33

32

31

1

2

3

4

5

6

7

8

9

10

ENA

TA1IN

TA2IN

TA3IN

TA4IN

RA5OUT

RA4OUT

RA3OUT

RA2OUT

RA1OUT

RA1IN

RA2IN

RA3IN

RA4IN

RA5IN

TA1OUT

TA2OUT

TA3OUT

TA4OUT

GND

TOP VIEW

MAX246

30

29

28

27

26

25

24

23

22

21

11

12

13

14

15

16

17

18

19

DIP

20

MAX246 FUNCTIONAL DESCRIPTION10 RECEIVERS 5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE) 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS2 CONTROL PINS ENABLE A-SIDE (ENA) ENABLE B-SIDE (ENB)

ENA ENB


MA

X2

20

–MA

X2

49


32 ______________________________________________________________________________________

400k

VCC

400k

GND

+5V

+5V

+5V

+5V

+5V

1

40

16

1µF

2

18

4

5k

5k

5k

5k

5k

5k

5k

5k

ENTA

TA1OUT

TA1IN

TA3OUT

TA3IN

6 RB5OUT

12 RA1IN

10 RA1OUT

13 RA2IN

9 RA2OUT

14 RA3IN

8 RA3OUT

15 RA4IN

7

20

RA4OUT

11

39

24

38

22

36

29

31

28

32

27

33

26

34

30ENRA

ENTB

TB1OUT

TB1IN

TB3OUT

TB3IN

RB1IN

5k

25RB5IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

ENRB

400k

+5V17

3

TA2OUT

TA2IN

+5V23

37

TB2OUT

TB2IN

400k

+5V19

5

TA4OUT

TA4IN

+5V21

35

TB4OUT

TB4IN

40 VCC

ENTB

TB1IN

TB2IN

TB3IN

TB4IN

RB4OUT

RB3OUT

RB2OUT

RB1OUT

RB1IN

RB2IN

RB3IN

RB4IN

RB5IN

TB1OUT

TB2OUT

TB3OUT

TB4OUT

39

38

37

36

35

34

33

32

31

1

2

3

4

5

6

7

8

9

10

ENTA

TA1IN

TA2IN

TA3IN

TA4IN

RB5OUT

RA4OUT

RA3OUT

RA2OUT

RA1OUT

RA1IN

RA2IN

RA3IN

RA4IN

TA1OUT

TA2OUT

TA3OUT

TA4OUT

GND

TOP VIEW

MAX247

30

29

28

27

26

25

24

23

22

21

11

12

13

14

15

16

17

18

19

DIP

20

ENRA ENRB

MAX247 FUNCTIONAL DESCRIPTION9 RECEIVERS 4 A-SIDE RECEIVERS 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVERr B-SIDE (ENTB)


MA

X2

20

–MA

X2

49


______________________________________________________________________________________ 33

400k



400k

GND

+5V

+5V

+5V

+5V

+5V

18

25

2423

2120

1

1µF

1µF

1µF1µF

1µF

14

3

16

5k

5k

5k

5k

5k

5k

5k

5k

ENTA

C2-C2+

C1-C1+

TA1OUT

TA1IN

TA3OUT

TA3IN

8 RA1IN

10 RA1OUT

7 RA2IN

11 RA2OUT

6 RA3IN

12 RA3OUT

5 RA4IN

13

19

RA4OUT

9

27

26

22

44

31

42

29

37

35

38

34

39

33

40

32

36ENRA

ENTB

V-

V+

TB1OUT

TB1IN

TB3OUT

TB3IN

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

ENRB

400k

+5V2

15

TA2OUT

TA2IN

+5V43

30

TB2OUT

TB2IN

400k

+5V4

17

TA4OUT

TA4IN

+5V41

28

TB4OUT

TB4IN

441234 404142435

21 24 2625 27 2822 2319 20

8

9

10

11

12

13

14

15

16

17 29

30

31

32

33

34

35

36

37

38

TA4IN

V CC

R A4IN

MAX248

PLCC

TOP VIEW

T A4O

UT

T A3O

UT

T A2O

UT

T A1O

UT

T B1O

UT

T B2O

UT

T B3O

UT

T A4O

UT

R B4IN

GND V+C1+

C2+

C1- V-C2-

T B4IN

ENTB

RB2IN

RB1IN

RB1OUT

RB2OUT

RB3OUT

RB4OUT

TB1IN

TB2IN

TB3IN

TA3IN

TA2IN

TA1IN

RA4OUT

RA3OUT

RA2OUT

RA1OUT

ENRA

RA1IN

7 39 RB3INRA2IN

6

18

R A3IN

ENRB

ENTA

MAX248 FUNCTIONAL DESCRIPTION8 RECEIVERS 4 A-SIDE RECEIVERS 4 B-SIDE RECEIVERS8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVER B-SIDE (ENTB)


MA

X2

20

–MA

X2

49


34 ______________________________________________________________________________________

400k



400k

400k

GND

+5V

+5V

+5V

+5V

+5V

+5V

+5V

18

25

2423

2120

1

1µF

1µF

1µF1µF

15

2

16

3

17

5k

5k

5k

5k

5k

5k

5k

5k

5k

5k

ENTA

C2-C2+

C1-C1+

TA1OUT

TA1IN

TA2OUT

TA2IN

TA3OUT

TA3IN

8 RA1IN

10 RA1OUT

7 RA2IN

11 RA2OUT

6 RA3IN

12 RA3OUT

5 RA4IN

13 RA4OUT

4 RA5IN

14

19

RA5OUT

9

27

26

22

44

30

43

29

42

28

37

35

38

34

39

33

40

32

41

31

36ENRA

ENTB

V-

V+

TB1OUT

TB1IN

TB2OUT

TB2IN

TB3OUT

TB3IN

RB1IN

RB1OUT

RB2IN

RB2OUT

RB3IN

RB3OUT

RB4IN

RB4OUT

RB5IN

RB5OUT

ENRB

441234 404142435

21 24 2625 27 2822 2319 20

8

9

10

11

12

13

14

15

16

17 29

30

31

32

33

34

35

36

37

38

V CC

R A4IN

R A5IN

MAX249

PLCC

TOP VIEW

T A3O

UT

T A2O

UT

T A1O

UT

T B1O

UT

T B2O

UT

T B3O

UT

R B4IN

R B5IN

GND V+C1+

C2+

C1- V-C2-

T B3IN

ENTB

RB2IN

RB1IN

RB1OUT

MAX249 FUNCTIONAL DESCRIPTION10 RECEIVERS 5 A-SIDE RECEIVERS 5 B-SIDE RECEIVERS6 TRANSMITTERS 3 A-SIDE TRANSMITTERS 3 B-SIDE TRANSMITTERS4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) ENABLE RECEIVER A-SIDE (ENTA) ENABLE RECEIVER B-SIDE (ENTB)

RB2OUT

RB3OUT

RB4OUT

RB5OUT

TB1IN

TB2INTA3IN

TA2IN

TA1IN

RA4OUT

RA5OUT

RA3OUT

RA2OUT

RA1OUT

ENRA

RA1IN

7 39 RB3INRA2IN

6

18

R A3IN

ENRB

ENTA

1µF


MA

X2

20

–MA

X2

49


______________________________________________________________________________________ 35

___________________________________________Ordering Information (continued)

PART

MAX222CPN 0°C to +70°C


18 Plastic DIP

MAX222CWN 0°C to +70°C 18 Wide SO


MAX222EPN -40°C to +85°C 18 Plastic DIP

MAX222EWN -40°C to +85°C 18 Wide SO

MAX222EJN -40°C to +85°C 18 CERDIP

MAX222MJN -55°C to +125°C 18 CERDIP

MAX223CAI 0°C to +70°C 28 SSOP

MAX223CWI 0°C to +70°C 28 Wide SO


MAX223EAI -40°C to +85°C 28 SSOP

MAX223EWI -40°C to +85°C 28 Wide SO

MAX225CWI 0°C to +70°C 28 Wide SO

MAX225EWI -40°C to +85°C 28 Wide SO

MAX230CPP 0°C to +70°C 20 Plastic DIP

MAX230CWP 0°C to +70°C 20 Wide SO


MAX230EPP -40°C to +85°C 20 Plastic DIP

MAX230EWP -40°C to +85°C 20 Wide SO

MAX230EJP -40°C to +85°C 20 CERDIP

MAX230MJP -55°C to +125°C 20 CERDIP

MAX231CPD 0°C to +70°C 14 Plastic DIP

MAX231CWE 0°C to +70°C 16 Wide SO

MAX231CJD 0°C to +70°C 14 CERDIP


MAX231EPD -40°C to +85°C 14 Plastic DIP

MAX231EWE -40°C to +85°C 16 Wide SO

MAX231EJD -40°C to +85°C 14 CERDIP

MAX231MJD -55°C to +125°C 14 CERDIP

MAX232CPE 0°C to +70°C 16 Plastic DIP

MAX232CSE 0°C to +70°C 16 Narrow SO



MAX232EPE -40°C to +85°C 16 Plastic DIP

MAX232ESE -40°C to +85°C 16 Narrow SO


MAX232EJE -40°C to +85°C 16 CERDIP

MAX232MJE -55°C to +125°C 16 CERDIP

MAX232MLP -55°C to +125°C 20 LCC

MAX232ACPE 0°C to +70°C 16 Plastic DIP

MAX232ACSE 0°C to +70°C 16 Narrow SO

MAX232ACWE 0°C to +70°C 16 Wide SO

MAX232AC/D

MAX232AEPE -40°C to +85°C 16 Plastic DIP

MAX232AESE

0°C to +70°C Dice*

-40°C to +85°C 16 Narrow SO

MAX232AEWE -40°C to +85°C 16 Wide SO

MAX232AEJE -40°C to +85°C 16 CERDIP

MAX232AMJE -55°C to +125°C 16 CERDIP

MAX232AMLP -55°C to +125°C 20 LCC

MAX233CPP 0°C to +70°C 20 Plastic DIP

MAX233EPP -40°C to +85°C 20 Plastic DIP

MAX233ACPP 0°C to +70°C 20 Plastic DIP

MAX233ACWP 0°C to +70°C 20 Wide SO

MAX233AEPP -40°C to +85°C 20 Plastic DIP

MAX233AEWP -40°C to +85°C 20 Wide SO

MAX234CPE 0°C to +70°C 16 Plastic DIP



MAX234EPE -40°C to +85°C 16 Plastic DIP


MAX234EJE -40°C to +85°C 16 CERDIP

MAX234MJE -55°C to +125°C 16 CERDIP

MAX235CPG 0°C to +70°C 24 Wide Plastic DIP

MAX235EPG -40°C to +85°C 24 Wide Plastic DIP

MAX235EDG -40°C to +85°C 24 Ceramic SB

MAX235MDG -55°C to +125°C 24 Ceramic SB

MAX236CNG 0°C to +70°C 24 Narrow Plastic DIP

MAX236CWG 0°C to +70°C 24 Wide SO


MAX236ENG -40°C to +85°C 24 Narrow Plastic DIP

MAX236EWG -40°C to +85°C 24 Wide SO

MAX236ERG -40°C to +85°C 24 Narrow CERDIP

MAX236MRG -55°C to +125°C 24 Narrow CERDIP





MAX237EWG -40°C to +85°C 24 Wide SO

MAX237ERG -40°C to +85°C 24 Narrow CERDIP

MAX237MRG -55°C to +125°C 24 Narrow CERDIP





* Contact factory for dice specifications.

MA

X2

20

–MA

X2

49

+5V-Powered, Multichannel RS-232Drivers/Receivers___________________________________________Ordering Information (continued)

* Contact factory for dice specifications.

18 CERDIP-55°C to +125°CMAX242MJN

18 CERDIP-40°C to +85°CMAX242EJN

18 Wide SO-40°C to +85°CMAX242EWN

18 Plastic DIP-40°C to +85°CMAX242EPN

Dice*0°C to +70°CMAX242C/D

18 Wide SO0°C to +70°CMAX242CWN

18 Plastic DIP0°C to +70°CMAX242CPN

20 SSOP0°C to +70°CMAX242CAP

28 Wide SO-40°C to +85°CMAX241EWI

28 SSOP-40°C to +85°CMAX241EAI


28 Wide SO0°C to +70°CMAX241CWI

28 SSOP0°C to +70°CMAX241CAI


44 Plastic FP0°C to +70°CMAX240CMH

24 Narrow CERDIP-55°C to +125°CMAX239MRG

24 Narrow CERDIP-40°C to +85°CMAX239ERG

24 Wide SO-40°C to +85°CMAX239EWG

24 Narrow Plastic DIP-40°C to +85°CMAX239ENG


24 Wide SO0°C to +70°CMAX239CWG

24 Narrow Plastic DIP0°C to +70°CMAX239CNG

24 Narrow CERDIP-55°C to +125°C

24 Wide SO

PIN-PACKAGETEMP. RANGE

-40°C to +85°C

MAX238MRG

24 Narrow CERDIP-40°C to +85°CMAX238ERG

MAX238EWG

PART

44 PLCC-40°C to +85°CMAX249EQH

44 PLCC0°C to +70°CMAX249CQH




40 Plastic DIP-40°C to +85°CMAX247EPL


40 Plastic DIP0°C to +70°CMAX247CPL










16 CERDIP-55°C to +125°CMAX243MJE

16 CERDIP-40°C to +85°CMAX243EJE

16 Wide SO-40°C to +85°CMAX243EWE

16 Narrow SO-40°C to +85°CMAX243ESE

16 Plastic DIP-40°C to +85°CMAX243EPE


16 Wide SO0°C to +70°C

16 Plastic DIP0°C to +70°C

MAX243CWE

16 Narrow SO0°C to +70°CMAX243CSE

MAX243CPE

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

36 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600

© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.


HEF4047

clxxiv

DATA SHEET

Product specificationFile under Integrated Circuits, IC04

January 1995

INTEGRATED CIRCUITS

HEF4047BMSIMonostable/astable multivibrator

For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B LogicFamily Specifications HEF, HEC

• The IC04 LOCMOS HE4000B LogicPackage Outlines/Information HEF, HEC

January 1995 2

Philips Semiconductors Product specification

Monostable/astable multivibratorHEF4047B

MSI

DESCRIPTION

The HEF4047B consists of a gatable astable multivibratorwith logic techniques incorporated to permit positive ornegative edge-triggered monostable multivibrator actionwith retriggering and external counting options.

Inputs include + TRIGGER, − TRIGGER, ASTABLE,ASTABLE, RETRIGGER and MR (Master Reset).Buffered outputs are O, O and OSCILLATOR OUTPUT. Inall modes of operation an external capacitor (Ct) must beconnected between CTC and RCTC, and an externalresistor (Rt) must be connected between RTC andRCTC (continued on next page).

FAMILY DATA, I DD LIMITS category MSI

See Family Specifications

Fig.1 Functional diagram.

January 1995 3



MSI

Astable operation is enabled by a HIGH level on theASTABLE input. The period of the square wave at O andO outputs is a function of the external componentsemployed. ‘True’ input pulses on the ASTABLE or‘complement’ pulses on the ASTABLE input, allow thecircuit to be used as a gatable multivibrator. TheOSCILLATOR OUTPUT period will be half of the O outputin the astable mode. However, a 50% duty factor is notguaranteed at this output.

In the monostable mode, positive edge-triggering isaccomplished by applying a leading-edge pulse to the+ TRIGGER input and a LOW level to the − TRIGGERinput. For negative edge-triggering, a trailing-edge pulse isapplied to the − TRIGGER and a HIGH level to the+ TRIGGER. Input pulses may be of any duration relativeto the output pulse. The multivibrator can be retriggered(on the leading-edge only) by applying a common pulse toboth the RETRIGGER and + TRIGGER inputs. In thismode the output pulse remains HIGH as long as the inputpulse period is shorter than the period determined by theRC components.

An external count down option can be implemented bycoupling O to an external ‘N’ counter and resetting thecounter with the trigger pulse. The counter output pulse isfed back to the ASTABLE input and has a duration equalto N times the period of the multivibrator. A HIGH level onthe MR input assures no output pulse during an ON-powercondition. This input can also be activated to terminate theoutput pulse at any time. In the monostable mode, a HIGHlevel or power-ON reset pulse must be applied to MR,whenever VDD is applied.

Fig.2 Pinning diagram.

HEF4047BP(N): 14-lead DIL; plastic

(SOT27-1)

HEF4047BD(F): 14-lead DIL; ceramic (cerdip)

(SOT73)

HEF4047BT(D): 14-lead SO; plastic

(SOT108-1)

( ): Package Designator North America

January 19954

Philips S

emiconductors

Product specification

Monostable/astable m

ultivibratorH

EF

4047BM

SI

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here inwhite to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

Fig.3 Logic diagram.

(1) Special input protection that allows operating input voltagesoutside the supply voltage lines. Compared to the standard inputprotection pin 3 is more sensitive to static discharge; extrahandling precautions are recommended.

January 1995 5



MSI

FUNCTIONAL CONNECTIONS

Notes

1. Input pulse to RESET of external counting chip; external counting chip output to pin 4.

2. In all cases, external resistor between pins 2 and 3, external capacitor between pins 1 and 3.

DC CHARACTERISTICSVSS = 0 V; inputs at VSS or VDD

FUNCTION

PINS CONNECTED TO OUTPUTPULSEFROMPINS

OUTPUTPERIOD

ORPULSE WIDTH

VDD VSSINPUTPULSE

astable multivibrator

free running 4, 5, 6, 14 7, 8, 9, 12 − 10, 11, 13 at pins 10, 11:

true gating 4, 6, 14 7, 8, 9, 12 5 10, 11, 13 tA = 4,40 RtCtat pin 13:tA = 2,20 RtCt

complement gating 6, 14 5, 7, 8, 9, 12 4 10, 11, 13

monostable multivibrator

pos. edge-triggering 4, 14 5, 6, 7, 9, 12 8 10, 11

neg. edge-triggering 4, 8, 14 5, 7, 9, 12 6 10, 11 at pins 10, 11:

retriggerable 4, 14 5, 6, 7, 9 8, 12 10, 11 tM = 2,48 RtCt

external count down(1) 14 5, 6, 7, 8, 9, 12 − 10, 11

VDDV

SYMBOL

Tamb (°C)

−40 + 25 + 85

MAX. MIN. MAX. MAX.

Leakage current

15 I3 0,3 − 0,3 1 µApin 3 atVDD or VSS

pin 3; output

transistor OFF

January 1995 6



MSI

AC CHARACTERISTICSVSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

VDDV

SYMBOL MIN. TYP. MAX.TYPICAL EXTRAPOLATION

FORMULA

Propagation delays

ASTABLE, ASTABLE → OSC. OUTPUT 5 95 190 68 ns + (0,55 ns/pF) CL

HIGH to LOW 10 tPHL 45 90 43 ns + (0,23 ns/pF) CL

15 30 60 22 ns + (0,16 ns/pF) CL

5 85 170 58 ns + (0,55 ns/pF) CL

LOW to HIGH 10 tPLH 40 80 29 ns + (0,23 ns/pF) CL

15 30 60 22 ns + (0,16 ns/pF) CL

ASTABLE, ASTABLE → O, O 5 150 300 123 ns + (0,55 ns/pF) CL


15 50 100 42 ns + (0,16 ns/pF) CL

5 130 260 103 ns + (0,55 ns/pF) CL


15 45 90 37 ns + (0,16 ns/pF) CL

+/− TRIGGER → O, O 5 160 320 133 ns + (0,55 ns/pF) CL


15 50 100 42 ns + (0,16 ns/pF) CL

5 155 310 128 ns + (0,55 ns/pF) CL


15 50 100 42 ns + (0,16 ns/pF) CL

+ TRIGGER, RETRIGGER → O 5 65 130 38 ns + (0,55 ns/pF) CL


15 25 50 17 ns + (0,16 ns/pF) CL

+ TRIGGER, RETRIGGER → O 5 95 190 68 ns + (0,55 ns/pF) CL


15 30 60 22 ns + (0,16 ns/pF) CL

MR → O 5 100 200 83 ns + (0,55 ns/pF) CL


15 35 70 27 ns + (0,16 ns/pF) CL

MR → O 5 100 200 83 ns + (0,55 ns/pF) CL


15 35 70 27 ns + (0,16 ns/pF) CL

Output transition times 5 60 120 10 ns + (1,0 ns/pF) CL

HIGH to LOW 10 tTHL 30 60 9 ns + (0,42 ns/pF) CL

15 20 40 6 ns + (0,28 ns/pF) CL

5 60 120 10 ns + (1,0 ns/pF) CL

LOW to HIGH 10 tTLH 30 60 9 ns + (0,42 ns/pF) CL

15 20 40 6 ns + (0,28 ns/pF) CL

January 1995 7



MSI

Minimum MR pulse 5 60 30

width; HIGH 10 tWMRH 30 15

15 20 10

Minimum input

pulse width; any 5 220 110

input exept MR 10 tW 100 50

15 70 35

VDDV

SYMBOL MIN. TYP. MAX.TYPICAL EXTRAPOLATION

FORMULA


General features:

• Monostable (one-shot) or astable (free-running)operation

• True and complemented buffered outputs

• Only one external R and C required

Monostable multivibrator features:

• Positive- or negative-edge triggering

• Output pulse width independent of trigger pulse duration

• Retriggerable option for pulse-width expansion

• Long pulse width possible using small RC componentsby means of external counter provision

• Fast recovery time essentially independent of pulsewidth

• Pulse-width accuracy maintained at duty cyclesapproaching 100%

Astable multivibrator features:

• Free-running or gatable operating modes

• 50% duty cycle

• Oscillator output available

January 1995 8



MSI

1. Astable mode design information

a. Unit-to-unit transfer-voltage variations

The following analysis presents worst-case variations from unit-to-unit as a function of transfer-voltage (VTR) shift for freerunning (astable) operation.

Values for tA are:

thus if tA = 4,40 RtCt is used, the maximum variation will be (+ 7,0%; −0,0%) at 10 V.

typ. : VTR = 0,5 VDD; tA = 4,40 RtCt

VDD = 5 or 10 Vmin. : VTR = 0,3 VDD; tA = 4,71 RtCt

max.: VTR = 0,7 VDD; tA = 4,71 RtCt

VDD = 15 Vmin. : VTR = 4 V; tA = 4,84 RtCt

max.: VTR = 11 V; tA = 4,84 RtCt

Fig.4 Astable mode waveforms.

t1 RtCt InVTR

VDD VTR+----------------------------–=

t2 RtCt InVDD VTR–

2VDD VTR–-------------------------------–=

tA 2 t1 t2+( ) 2RtCt InVTR( ) VDD VTR–( )

VDD VTR+( ) 2VDD VTR–( )------------------------------------------------------------------------- , where tA Astable mode pulse width.=–==

January 1995 9



MSI

b. Variations due to changes in VDD

In addition to variations from unit-to-unit, the astable period may vary as a function of frequency with respect to VDD.

Typical variations are presented graphically in Figs 5 and 6 with 10 V as a reference.

CURVE fOkHz

CtpF

RtkΩ

A 10 100 220

B 5 100 470

C 1 1000 220

Fig.5 Typical O and O period accuracy as a function of supply voltage; astable mode; Tamb = 25 °C.

January 1995 10



MSI

CURVE fOkHz

CtpF

RtkΩ

A 500 10 47

B 225 100 10

C 100 100 22

D 50 100 47

Fig.6 Typical O and O period accuracy as a function of supply voltage; astable mode; Tamb = 25 °C.

January 1995 11



MSI

2. Monostable mode design information

The following analysis presents worst case variations from unit-to-unit as a function of transfer-voltage (VTR) shift forone-shot (monostalbe) operation.

Values for tM are:

Note

1. In the astable mode, the first positive half cycle has a duration of tM; succeeding durations are 1⁄2 tA.

thus if tM = 2,48 RtCt is used, the maximum variation will be (+ 12%; −0,0%) at 10 V.

typ. : VTR = 0,5 VDD; tM = 2,48 RtCt

VDD = 5 to10 Vmin. : VTR = 0,3 VDD; tM = 2,78 RtCt

max.: VTR = 0,7 VDD; tM = 2,52 RtCt

VDD = 15 Vmin. : VTR = 4 V; tM = 2,88 RtCt

max.: VTR = 11 V; tM = 2,56 RtCt

Fig.7 Monostable waveforms.

t1‘ RtCt InVTR

2VDD--------------–=

tM t1' t2+( )=

tM RtCt InVTR( ) VDD VTR–( )

2VDD VTR–( ) 2VDD( )------------------------------------------------------------ , where tM Monostable mode pulse width.=–=

January 1995 12



MSI

3. Retrigger mode operation

The HEF4047B can be used in the retrigger mode to extend the output pulse duration, or to compare the frequency ofan input signal with that of the internal oscillator. In the retrigger mode the input pulse is applied to pins 8 and 12, andthe output is taken from pin 10 or 11. Normal monostable action is obtained when one retrigger pulse is applied (Fig.8).Extended pulse duration is obtained when more than one pulse is applied. For two input pulses, tRE = t1’ + t1 + 2t2.For more than two pulses, tRE (output O), terminates at some variable time, tD, after the termination of the last retriggerpulse; tD is variable because tRE (output O) terminates after the second positive edge of the oscillator output appears atflip-flop 4.

4. External counter option

Time tM can be extended by any amount with the use of external counting circuitry. Advantages include digitallycontrolled pulse duration, small timing capacitors for long time periods, and extremely fast recovery time. A typicalimplementation is shown in Fig.9.The pulse duration at the output is:

Where text = pulse duration of the circuitry, and N is the number of counts used.

Fig.8 Retrigger mode waveforms.

text N 1–( ) tA( ) tM 1 2 tA⁄+( )+=

Fig.9 Implementation of external counter option.

January 1995 13



MSI

5. Timing component limitations

The capacitor used in the circuit should be non-polarized and have low leakage (i.e. the parallel resistance of thecapacitor should be an order of magnitude greater than the external resistor used).There is no upper or lower limit for either Rt or Ct value to maintain oscillation.However, in consideration of accuracy, Ct must be much larger than the inherent stray capacitance in the system (unlessthis capacitance can be measured and taken into account).Rt must be much larger than the LOCMOS ‘ON’ resistance in series with it, which typically is hundreds of ohms.

The recommended values for Rt and Ct to maintain agreement with previously calculated formulae without trimmingshould be:

Ct ≥ 100 pF, up to any practical value,10 kΩ ≤ Rt ≤ 1 MΩ.

6. Power consumption

In the standby mode (monostable or astable), power dissipation will be a function of leakage current in the circuit.For dynamic operation, the power needed to charge the external timing capacitor Ct is given by the following formulae:

Because the power dissipation does not depend on Rt, a design for minimum power dissipation would be a small valueof Ct. The value of R would depend on the desired period (within the limitations discussed previously).Typical power consumption in astable mode is shown in Figs 10, 11 and 12.

Astable mode: P = 2 Ct V2 f (f at output pin 13)

P = 4 Ct V2 f (f at output pins 10 and 11)

Monostable mode: P =2 9 Ct V

2, duty cycle( )

T--------------------------------------------------------------------- f at output pins 10 and 11( )

January 1995 14



MSI

Fig.10 Power consumption as a function of the output frequency at O or O; VDD = 5 V; astable mode.


January 1995 15



MSI



AT89C51

cxc

8-bit Microcontroller with 4K Bytes Flash

AT89C51

Not Recommended

Features• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-level Program Memory Lock• 128 x 8-bit Internal RAM• 32 Programmable I/O Lines• Two 16-bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low-power Idle and Power-down Modes

DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. The on-chipFlash allows the program memory to be reprogrammed in-system or by a conven-tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control applications.

1

PQFP/TQFP

1234567891011

3332313029282726252423

P1.5P1.6P1.7RST

(RXD) P3.0NC

(TXD) P3.1(INT0) P3.2(INT1) P3.3

(T0) P3.4(T1) P3.5

PO.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPNCALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)

44 43 42 41 40 39 38 37 36 35 34

12 13 14 15 16 17 18 19 20 21 22

(WR

)P3.

6(R

D)

P3.

7X

TA

L2X

TA

L1G

ND

GN

D(A

8) P

2.0

(A9)

P2.

1(A

10)

P2.

2(A

11)

P2.

3(A

12)

P2.

4

P1.

4P

1.3

P1.

2 P

1.1

(T2

EX

)P

1.0

(T2)

NC

VC

CP

0.0

(AD

0)P

0.1

(AD

1)P

0.2

(AD

2)P

0.3

(AD

3)

PDIP

1234567891011121314151617181920

4039383736353433323130292827262524232221

P1.0 P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST

(RXD) P3.0(TXD) P3.1(INT0) P3.2(INT1) P3.3

(T0) P3.4(T1) P3.5

(WR) P3.6(RD) P3.7

XTAL2XTAL1

GND

VCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)P2.4 (A12)P2.3 (A11)P2.2 (A10)P2.1 (A9)P2.0 (A8)

Rev. 0265G–02/00

for New Designs. Use AT89S51.

Pin Configurations

PLCC

7891011121314151617

3938373635343332313029

P1.5P1.6P1.7RST

(RXD) P3.0NC

(TXD) P3.1(INT0) P3.2(INT1) P3.3

(T0) P3.4(T1) P3.5

PO.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPNCALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)

6 5 4 3 2 1 44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

(WR

)P3.

6(R

D)

P3.

7X

TA

L2X

TA

L1G

ND

NC

(A8)

P2.

0(A

9) P

2.1

(A10

) P

2.2

(A11

) P

2.3

(A12

) P

2.4

P1.

4P

1.3

P1.

2 P

1.1

P1.

0N

CV

CC

P0.

0 (A

D0)

P0.

1 (A

D1)

P0.

2 (A

D2)

P0.

3 (A

D3)

AT89C512

Block Diagram

PORT 2 DRIVERS

PORT 2LATCH

P2.0 - P2.7

FLASHPORT 0LATCHRAM

PROGRAMADDRESSREGISTER

BUFFER

PCINCREMENTER

PROGRAMCOUNTER

DPTR

RAM ADDR.REGISTER

INSTRUCTIONREGISTER

BREGISTER

INTERRUPT, SERIAL PORT,AND TIMER BLOCKS

STACKPOINTERACC

TMP2 TMP1

ALU

PSW

TIMINGAND

CONTROL

PORT 3LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1LATCH

PORT 1 DRIVERS

P1.0 - P1.7

OSC

GND

VCC

PSEN

ALE/PROG

EA / VPP

RST

PORT 0 DRIVERS

P0.0 - P0.7

AT89C51

The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock cir-cuitry. In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external pro-gram and data memory. In this mode P0 has internalpullups.

Port 0 also receives the code bytes during Flash program-ming, and outputs the code bytes during programverification. External pullups are required during programverification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes duringFlash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses toexternal data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data mem-ory that use 8-bit addresses (MOVX @ RI), Port 2 emits thecontents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and somecontrol signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will sourcecurrent (IIL) because of the pullups.

Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:

Port 3 also receives some control signals for Flash pro-gramming and verification.

RST

Reset input. A high on this pin for two machine cycles whilethe oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byteof the address during accesses to external memory. Thispin is also the program pulse input (PROG) during Flashprogramming.

In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external tim-ing or clocking purposes. Note, however, that one ALE

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR (external data memory write strobe)

P3.7 RD (external data memory read strobe)

3

pulse is skipped during each access to external DataMemory.

If desired, ALE operation can be disabled by setting bit 0 ofSFR location 8EH. With the bit set, ALE is active only dur-ing a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro-gram memory.

When the AT89C51 is executing code from external pro-gram memory, PSEN is activated twice each machinecycle, except that two PSEN activations are skipped duringeach access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND inorder to enable the device to fetch code from external pro-gram memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will beinternally latched on reset.

EA should be strapped to VCC for internal programexecutions.

This pin also receives the 12-volt programming enable volt-age (VPP) during Flash programming, for parts that require12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to theinternal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use asan on-chip oscillator, as shown in Figure 1. Either a quartzcrystal or ceramic resonator may be used. To drive thedevice from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the externalclock signal, since the input to the internal clocking circuitryis through a divide-by-two flip-flop, but minimum and maxi-mum voltage high and low time specifications must beobserved.

Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked bysoftware. The content of the on-chip RAM and all the spe-cial functions registers remain unchanged during thismode. The idle mode can be terminated by any enabledinterrupt or by a hardware reset.

It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execu-tion, from where it left off, up to two machine cycles beforethe internal reset algorithm takes control. On-chip hardwareinhibits access to internal RAM in this event, but access tothe port pins is not inhibited. To eliminate the possibility ofan unexpected write to a port pin when Idle is terminated byreset, the instruction following the one that invokes Idleshould not be one that writes to a port pin or to externalmemory.

Figure 1. Oscillator Connections

Note: C1, C2 = 30 pF ± 10 pF for Crystals= 40 pF ± 10 pF for Ceramic Resonators

C2XTAL2

GND

XTAL1C1

Status of External Pins During Idle and Power-down ModesMode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

AT89C514

AT89C51

Figure 2. External Clock Drive Configuration

Power-down Mode In the power-down mode, the oscillator is stopped, and theinstruction that invokes power-down is the last instructionexecuted. The on-chip RAM and Special Function Regis-

ters retain their values until the power-down mode isterminated. The only exit from power-down is a hardwarereset. Reset redefines the SFRs but does not change theon-chip RAM. The reset should not be activated before VCCis restored to its normal operating level and must be heldactive long enough to allow the oscillator to restart andstabilize.

Program Memory Lock Bits On the chip are three lock bits which can be left unpro-grammed (U) or can be programmed (P) to obtain theadditional features listed in the table below.

When lock bit 1 is programmed, the logic level at the EA pinis sampled and latched during reset. If the device is pow-ered up without a reset, the latch initializes to a randomvalue, and holds that value until reset is activated. It is nec-essary that the latched value of EA be in agreement withthe current logic level at that pin in order for the device tofunction properly.

Lock Bit Protection ModesProgram Lock Bits

Protection TypeLB1 LB2 LB3

1 U U U No program lock features

2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled

3 P P U Same as mode 2, also verify is disabled

4 P P P Same as mode 3, also external execution is disabled

5

Programming the Flash The AT89C51 is normally shipped with the on-chip Flashmemory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interfaceaccepts either a high-voltage (12-volt) or a low-voltage(VCC) program enable signal. The low-voltage program-ming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltageprogramming mode is compatible with conventional third-party Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage orlow-voltage programming mode enabled. The respectivetop-side marking and device signature codes are listed inthe following table.

The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memorymust be erased using the Chip Erase Mode.

Programming Algorithm: Before programming theAT89C51, the address, data and control signals should beset up according to the Flash programming mode table andFigure 3 and Figure 4. To program the AT89C51, take thefollowing steps.

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V for the high-voltage program-ming mode.

5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address

and data for the entire array or until the end of the object file is reached.

Data Polling: The AT89C51 features Data Polling to indi-cate the end of a write cycle. During a write cycle, anattempted read of the last byte written will result in the com-plement of the written datum on PO.7. Once the write cyclehas been completed, true data are valid on all outputs, andthe next cycle may begin. Data Polling may begin any timeafter a write cycle has been initiated.

Ready/Busy: The progress of byte programming can alsobe monitored by the RDY/BSY output signal. P3.4 is pulledlow after ALE goes high during programming to indicateBUSY. P3.4 is pulled high again when programming isdone to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not beenprogrammed, the programmed code data can be read backvia the address and data lines for verification. The lock bitscannot be verified directly. Verification of the lock bits isachieved by observing that their features are enabled.

Chip Erase: The entire Flash array is erased electricallyby using the proper combination of control signals and byholding ALE/PROG low for 10 ms. The code array is writtenwith all “1”s. The chip erase operation must be executedbefore the code memory can be re-programmed.

Reading the Signature Bytes: The signature bytes areread by the same procedure as a normal verification oflocations 030H, 031H, and 032H, except that P3.6 andP3.7 must be pulled to a logic low. The values returned areas follows.

(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming

Programming InterfaceEvery code byte in the Flash array can be written and theentire array can be erased by using the appropriate combi-nation of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself tocompletion.

All major programming vendors offer worldwide support forthe Atmel microcontroller series. Please contact your localprogramming vendor for the appropriate software revision.

VPP = 12V VPP = 5V

Top-side Mark AT89C51xxxx

yyww

AT89C51xxxx-5

yyww

Signature (030H) = 1EH

(031H) = 51H(032H) =F FH

(030H) = 1EH

(031H) = 51H(032H) = 05H

AT89C516

AT89C51

Note: 1. Chip Erase requires a 10 ms PROG pulse.

Figure 3. Programming the Flash Figure 4. Verifying the Flash

Flash Programming ModesMode RST PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7

Write Code Data H L H/12V L H H H

Read Code Data H L H H L L H H

Write Lock Bit - 1 H L H/12V H H H H

Bit - 2 H L H/12V H H L L

Bit - 3 H L H/12V H L H L

Chip Erase H L H/12V H L L L

Read Signature Byte H L H H L L L L

(1)

P1

P2.6

P3.6

P2.0 - P2.3

A0 - A7ADDR.

OOOOH/OFFFH

T

SEE FLASHPROGRAMMINGMODES ABLE

3-24 MHz

A8 - A11P0

+5V

P2.7

PGMDATA

PROG

V /VIH PP

VIH

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

VCC

AT89C51

P1

P2.6

P3.6

P2.0 - P2.3

A0 - A7ADDR.

OOOOH/0FFFH

3-24 MHz

A8 - A11P0

+5V

P2.7

PGM DATA(USE 10KPULLUPS)

VIH

VIH

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

VCC

AT89C51

T

SEE FLASHPROGRAMMINGMODES ABLE

7

Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V)

Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V)

tGLGHtGHSL

tAVGL

tSHGL

tDVGLtGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7P2.0 - P2.3

ALE/PROG

PORT 0

LOGIC 1LOGIC 0EA/VPP

VPP

P2.7(ENABLE)

P3.4(RDY/BSY)

PROGRAMMINGADDRESS

VERIFICATIONADDRESS

DATA IN DATA OUT

tGLGH

tAVGL

tSHGL

tDVGLtGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7P2.0 - P2.3

ALE/PROG

PORT 0

LOGIC 1LOGIC 0EA/VPP

P2.7(ENABLE)

P3.4(RDY/BSY)

PROGRAMMINGADDRESS

VERIFICATIONADDRESS

DATA IN DATA OUT

AT89C518

AT89C51

Note: 1. Only used in 12-volt programming mode.

Flash Programming and Verification Characteristics TA = 0°C to 70°C, VCC = 5.0 ± 10%

Symbol Parameter Min Max Units

VPP(1) Programming Enable Voltage 11.5 12.5 V

IPP(1) Programming Enable Current 1.0 mA

1/tCLCL Oscillator Frequency 3 24 MHz

tAVGL Address Setup to PROG Low 48tCLCL

tGHAX Address Hold after PROG 48tCLCL

tDVGL Data Setup to PROG Low 48tCLCL

tGHDX Data Hold after PROG 48tCLCL

tEHSH P2.7 (ENABLE) High to VPP 48tCLCL

tSHGL VPP Setup to PROG Low 10 µs

tGHSL(1) VPP Hold after PROG 10 µs

tGLGH PROG Width 1 110 µs

tAVQV Address to Data Valid 48tCLCL

tELQV ENABLE Low to Data Valid 48tCLCL

tEHQZ Data Float after ENABLE 0 48tCLCL

tGHBL PROG High to BUSY Low 1.0 µs

tWC Byte Write Cycle Time 2.0 ms

9

Absolute Maximum Ratings*

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum IOL per 8-bit port: Port 0: 26 mAPorts 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mAIf IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

2. Minimum VCC for Power-down is 2V.

Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage ............................................ 6.6V

DC Output Current...................................................... 15.0 mA

DC CharacteristicsTA = -40°C to 85°C, VCC = 5.0V ± 20% (unless otherwise noted)

Symbol Parameter Condition Min Max Units

VIL Input Low-voltage (Except EA) -0.5 0.2 VCC - 0.1 V

VIL1 Input Low-voltage (EA) -0.5 0.2 VCC - 0.3 V

VIH Input High-voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V

VIH1 Input High-voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V

VOL Output Low-voltage(1) (Ports 1,2,3) IOL = 1.6 mA 0.45 V

VOL1Output Low-voltage(1)

(Port 0, ALE, PSEN)IOL = 3.2 mA 0.45 V

VOHOutput High-voltage(Ports 1,2,3, ALE, PSEN)

IOH = -60 µA, VCC = 5V ± 10% 2.4 V

IOH = -25 µA 0.75 VCC V

IOH = -10 µA 0.9 VCC V

VOH1Output High-voltage(Port 0 in External Bus Mode)

IOH = -800 µA, VCC = 5V ± 10% 2.4 V

IOH = -300 µA 0.75 VCC V

IOH = -80 µA 0.9 VCC V

IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA

ITLLogical 1 to 0 Transition Current (Ports 1,2,3)

VIN = 2V, VCC = 5V ± 10% -650 µA

ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA

RRST Reset Pull-down Resistor 50 300 KΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF

ICC

Power Supply CurrentActive Mode, 12 MHz 20 mA

Idle Mode, 12 MHz 5 mA

Power-down Mode(2)VCC = 6V 100 µA

VCC = 3V 40 µA

AT89C5110

AT89C51

AC CharacteristicsUnder operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.

External Program and Data Memory Characteristics

Symbol Parameter

12 MHz Oscillator 16 to 24 MHz Oscillator

UnitsMin Max Min Max


tLHLL ALE Pulse Width 127 2tCLCL-40 ns

tAVLL Address Valid to ALE Low 43 tCLCL-13 ns

tLLAX Address Hold after ALE Low 48 tCLCL-20 ns

tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns

tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns

tPLPH PSEN Pulse Width 205 3tCLCL-20 ns

tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-45 ns

tPXIX Input Instruction Hold after PSEN 0 0 ns

tPXIZ Input Instruction Float after PSEN 59 tCLCL-10 ns

tPXAV PSEN to Address Valid 75 tCLCL-8 ns

tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns

tPLAZ PSEN Low to Address Float 10 10 ns

tRLRH RD Pulse Width 400 6tCLCL-100 ns

tWLWH WR Pulse Width 400 6tCLCL-100 ns

tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns

tRHDX Data Hold after RD 0 0 ns

tRHDZ Data Float after RD 97 2tCLCL-28 ns

tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns

tAVDV Address to Valid Data In 585 9tCLCL-165 ns

tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns

tAVWL Address to RD or WR Low 203 4tCLCL-75 ns

tQVWX Data Valid to WR Transition 23 tCLCL-20 ns

tQVWH Data Valid to WR High 433 7tCLCL-120 ns

tWHQX Data Hold after WR 33 tCLCL-20 ns

tRLAZ RD Low to Address Float 0 0 ns

tWHLH RD or WR High to ALE High 43 123 tCLCL-20 tCLCL+25 ns

11

External Program Memory Read Cycle

External Data Memory Read Cycle

tLHLL

tLLIV

tPLIV

tLLAXtPXIZ

tPLPH

tPLAZtPXAV

tAVLL tLLPL

tAVIV

tPXIX

ALE

PSEN

PORT 0

PORT 2 A8 - A15

A0 - A7 A0 - A7

A8 - A15

INSTR IN

tLHLL

tLLDV

tLLWL

tLLAX

tWHLH

tAVLL

tRLRH

tAVDV

tAVWL

tRLAZ tRHDX

tRLDV tRHDZ

A0 - A7 FROM RI OR DPL

ALE

PSEN

RD

PORT 0

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA IN INSTR IN

AT89C5112

AT89C51

External Data Memory Write Cycle

External Clock Drive Waveforms

External Clock DriveSymbol Parameter Min Max Units


tCLCL Clock Period 41.6 ns

tCHCX High Time 15 ns

tCLCX Low Time 15 ns

tCLCH Rise Time 20 ns

tCHCL Fall Time 20 ns

tLHLL

tLLWL

tLLAX

tWHLH

tAVLL

tWLWH

tAVWL

tQVWXtQVWH

tWHQX

A0 - A7 FROM RI OR DPL

ALE

PSEN

WR

PORT 0

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA OUT INSTR IN

tCHCX

tCHCX

tCLCX

tCLCL

tCHCLtCLCHV - 0.5VCC

0.45V0.2 V - 0.1VCC

0.7 VCC

13

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.

Float Waveforms(1)

Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs.

Serial Port Timing: Shift Register Mode Test Conditions(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)

Symbol Parameter

12 MHz Osc Variable Oscillator Units

Min Max Min Max

tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs

tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns

tXHQX Output Data Hold after Clock Rising Edge 50 2tCLCL-117 ns

tXHDX Input Data Hold after Clock Rising Edge 0 0 ns

tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

tXHDV

tQVXH

tXLXL

tXHDX

tXHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

0

0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

SET TI

SET RI

8

VALID VALIDVALID VALIDVALID VALIDVALID VALID

0.45V

TEST POINTS

V - 0.5VCC 0.2 V + 0.9VCC

0.2 V - 0.1VCC

VLOAD+ 0.1V

Timing ReferencePoints

V

LOAD- 0.1V

LOAD

V VOL+ 0.1V

VOL- 0.1V

AT89C5114

AT89C51

Ordering InformationSpeed(MHz)

PowerSupply Ordering Code Package Operation Range

12 5V ± 20% AT89C51-12AC 44A Commercial

AT89C51-12JC 44J (0° C to 70° C)

AT89C51-12PC 40P6

AT89C51-12QC 44Q

AT89C51-12AI 44A Industrial

AT89C51-12JI 44J (-40° C to 85° C)

AT89C51-12PI 40P6

AT89C51-12QI 44Q


AT89C51-16JC 44J (0° C to 70° C)

AT89C51-16PC 40P6

AT89C51-16QC 44Q


AT89C51-16JI 44J (-40° C to 85° C)

AT89C51-16PI 40P6

AT89C51-16QI 44Q


AT89C51-20JC 44J (0° C to 70° C)

AT89C51-20PC 40P6

AT89C51-20QC 44Q


AT89C51-20JI 44J (-40° C to 85° C)

AT89C51-20PI 40P6

AT89C51-20QI 44Q


AT89C51-24JC 44J (0° C to 70° C)

AT89C51-24PC 40P6

AT89C51-24QC 44Q


AT89C51-24JI 44J (-40° C to 85° C)

AT89C51-24PI 40P6

AT89C51-24QI 44Q

15

Package Type

44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

40P6 40-lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44Q 44-lead, Plastic Gull Wing Quad Flatpack (PQFP)

Packaging Information

Controlling dimension: millimeters

1.20(0.047) MAX

10.10(0.394)9.90(0.386)

SQ

12.21(0.478)11.75(0.458)

SQ

0.75(0.030)0.45(0.018)

0.15(0.006)0.05(0.002)

0.20(.008)0.09(.003)

07

0.80(0.031) BSC

PIN 1 ID

0.45(0.018)0.30(0.012)

JEDEC STANDARD MS-026 ACB

AT89C5116

.045(1.14) X 45° PIN NO. 1IDENTIFY

.045(1.14) X 30° - 45° .012(.305).008(.203)

.021(.533)

.013(.330)

.630(16.0)

.590(15.0)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29).180(4.57).165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)SQ

SQ

2.07(52.6)2.04(51.8) PIN

1

.566(14.4)

.530(13.5)

.090(2.29)MAX

.005(.127)MIN

.065(1.65)

.015(.381)

.022(.559)

.014(.356).065(1.65).041(1.04)

015

REF

.690(17.5)

.610(15.5)

.630(16.0)

.590(15.0)

.012(.305)

.008(.203)

.110(2.79)

.090(2.29)

.161(4.09)

.125(3.18)

SEATINGPLANE

.220(5.59)MAX

1.900(48.26) REF

Controlling dimension: millimeters

13.45 (0.525)12.95 (0.506)

0.50 (0.020)0.35 (0.014)

SQ

PIN 1 ID

0.80 (0.031) BSC

10.10 (0.394)9.90 (0.386) SQ

070.17 (0.007)

0.13 (0.005)

1.03 (0.041)0.78 (0.030)

2.45 (0.096) MAX

0.25 (0.010) MAX

44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flatpack (TQFP)Dimensions in Millimeters and (Inches)*

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-018 AC

40P6, 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)Dimensions in Inches and (Millimeters)

44Q, 44-lead, Plastic Quad Flat Package (PQFP)Dimensions in Millimeters and (Inches)*JEDEC STANDARD MS-022 AB

© Atmel Corporation 2000.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility forany errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time withoutnotice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products arenot authorized for use as critical components in life support devices or systems.

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XC9536PC

ccviii

9

Features• 5 ns pin-to-pin logic delays on all pins• fCNT to 100 MHz

• 36 macrocells with 800 usable gates• Up to 34 user I/O pins• 5 V in-system programmable (ISP)

- Endurance of 10,000 program/erase cycles- Program/erase over full commercial voltage and

temperature range• Enhanced pin-locking architecture• Flexible 36V18 Function Block

- 90 product terms drive any or all of 18 macrocells within Function Block

- Global and product term clocks, output enables, set and reset signals

• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support

• Programmable power reduction mode in each macrocell

• Slew rate control on individual outputs• User programmable ground pin capability• Extended pattern security features for design protection• High-drive 24 mA outputs• 3.3 V or 5 V I/O capability• Advanced CMOS 5V FastFLASH technology• Supports parallel programming of more than one

XC9500 concurrently• Available in 44-pin PLCC, 44-pin VQFP, and 48-pin

CSP packages

DescriptionThe XC9536 is a high-performance CPLD providingadvanced in-system programming and test capabilities forgeneral purpose logic integration. It is comprised of two36V18 Function Blocks, providing 800 usable gates withpropagation delays of 5 ns. See Figure 2 for the architec-ture overview.

Power ManagementPower dissipation can be reduced in the XC9536 by config-uring macrocells to standard or low-power modes of opera-tion. Unused macrocells are turned off to minimize powerdissipation.

Operating current for each design can be approximated forspecific operating conditions using the following equation:

ICC (mA) =

MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f

Where:

MCHP = Macrocells in high-performance mode

MCLP = Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

Figure 1 shows a typical calculation for the XC9536 device.

1

XC9536 In-System Programmable CPLD

December 4, 1998 (Version 5.0) 1 1* Product Specification

Clock Frequency (MHz)

Typ

ical

I CC

(m

A)

0 50

(50)

(30)

(83)

(50)

100

High Performance

Low Power

X5920

Figure 1: Typical ICC vs. Frequency For XC9536

December 4, 1998 (Version 5.0) 1


In-System Programming ControllerJTAGController

I/OBlocks

FunctionBlock 1

Macrocells1 to 18

Macrocells1 to 18

JTAG Port

3

36

I/O/GTS

I/O/GSR

I/O/GCK

I/O

I/O

I/O

I/O

2

1

I/O

I/O

I/O

I/O

3

X5919

1

FunctionBlock 2

36

18

18

Fas

tCO

NN

EC

T S

witc

h M

atrix

Figure 2: XC9536 Architecture

Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

2 December 4, 1998 (Version 5.0)


Absolute Maximum Ratings

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions1

Note 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics

Symbol Parameter Value Units

VCC Supply voltage relative to GND -0.5 to 7.0 VVIN DC input voltage relative to GND -0.5 to VCC + 0.5 VVTS Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 VTSTG Storage temperature -65 to +150 °CTSOL Max soldering temperature (10 s @ 1/16 in = 1.5 mm) +260 °C


VCCINT Supply voltage for internal logic and input buffer 4.75(4.5)

5.25(5.5)

V

VCCIO Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) VSupply voltage for output drivers for 3.3 V operation 3.0 3.6 V

VIL Low-level input voltage 0 0.80 VVIH High-level input voltage 2.0 VCCINT +0.5 VVO Output voltage 0 VCCIO V


tDR Data Retention 20 - Years

NPE Program/Erase Cycles 10,000 - Cycles



DC Characteristics Over Recommended Operating Conditions

AC Characteristics

Note: 1. fCNT is the fastest 16-bit counter frequency available. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.

2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

Symbol Parameter Test Conditions Min Max Units

VOH Output high voltage for 5 V operation IOH = -4.0 mA VCC = Min

2.4 V

Output high voltage for 3.3 V operation IOH = -3.2 mA VCC = Min

2.4 V

VOL Output low voltage for 5 V operation IOL = 24 mA VCC = Min

0.5 V

Output low voltage for 3.3 V operation IOL = 10 mA VCC = Min

0.4 V

IIL Input leakage current VCC = MaxVIN = GND or VCC

±10.0 µA

IIH I/O high-Z leakage current VCC = MaxVIN = GND or VCC

±10.0 µA

CIN I/O capacitance VIN = GNDf = 1.0 MHz

10.0 pF

ICC Operating Supply Current (low power mode, active)

VI = GND, No loadf = 1.0 MHz

30 (Typ)mA

Symbol ParameterXC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15

UnitsMin Max Min Max Min Max Min Max Min Max

tPD I/O to output valid 5.0 6.0 7.5 10.0 15.0 nstSU I/O setup time before GCK 3.5 3.5 4.5 6.0 8.0 nstH I/O hold time after GCK 0.0 0.0 0.0 0.0 0.0 nstCO GCK to output valid 4.0 4.0 4.5 6.0 8.0 nsfCNT

1 16-bit counter frequency 100.0 100.0 83.3 66.7 55.6 MHzfSYSTEM

2 Multiple FB internal operating frequency 100.0 100.0 83.3 66.7 55.6 MHztPSU I/O setup time before p-term clock input 0.5 0.5 0.5 2.0 4.0 nstPH I/O hold time after p-term clock input 3.0 3.0 4.0 4.0 4.0 nstPCO P-term clock to output valid 7.0 7.0 8.5 10.0 12.0 nstOE GTS to output valid 5.0 5.0 5.5 6.0 11.0 nstOD GTS to output disable 5.0 5.0 5.5 6.0 11.0 nstPOE Product term OE to output enabled 9.0 9.0 9.5 10.0 14.0 nstPOD Product term OE to output disabled 9.0 9.0 9.5 10.0 14.0 nstWLH GCK pulse width (High or Low) 4.0 4.0 4.0 4.5 5.5 ns



Internal Timing Parameters

Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.

Symbol ParameterXC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15

UnitsMin Max Min Max Min Max Min Max Min Max

Buffer DelaystIN Input buffer delay 1.5 1.5 2.5 3.5 4.5 nstGCK GCK buffer delay 1.5 1.5 1.5 2.5 3.0 nstGSR GSR buffer delay 4.0 4.0 4.5 6.0 7.5 nstGTS GTS buffer delay 5.0 5.0 5.5 6.0 11.0 nstOUT Output buffer delay 2.0 2.0 2.5 3.0 4.5 nstEN Output buffer enable/disable delay 0.0 0.0 0.0 0.0 0.0 nsProduct Term Control DelaystPTCK Product term clock delay 3.0 3.0 3.0 3.0 2.5 nstPTSR Product term set/reset delay 1.0 1.0 2.0 2.5 3.0 nstPTTS Product term 3-state delay 5.5 5.5 4.5 3.5 5.0 nsInternal Register and Combinatorial delaystPDI Combinatorial logic propagation delay 0.5 1.5 0.5 1.0 3.0 nstSUI Register setup time 2.5 2.5 1.5 2.5 3.5 nstHI Register hold time 1.0 1.0 3.0 3.5 4.5 nstCOI Register clock to output valid time 0.5 0.5 0.5 0.5 0.5 nstAOI Register async. S/R to output delay 6.0 6.0 6.5 7.0 8.0 nstRAI Register async. S/R recovery before clock 5.0 5.0 7.5 10.0 10.0 nstLOGI Internal logic delay 1.0 1.0 2.0 2.5 3.0 nstLOGILP Internal low power logic delay 9.0 9.0 10.0 11.0 11.5 nsFeedback DelaystF FastCONNECT matrix feeback delay 6.0 6.0 8.0 9.5 11.0 nsTime AdderstPTA

3 Incremental Product Term Allocator delay 0.8 0.8 1.0 1.0 1.0 nstSLEW Slew-rate limited delay 3.5 3.5 4.0 4.5 5.0 ns

R1

VTEST

CLR2

Device Output

Output Type VTEST

5.0 V

3.3 V

R1

160 Ω260 Ω

R2

120 Ω360 Ω

CL

35 pF

35 pF

X5906

VCCIO

5.0 V

3.3 V

Figure 3: AC Load Circuit



XC9536 I/O Pins

XC9536 Global, JTAG and Power Pins

FunctionBlock Macrocell PC44 VQ44 CS48 BScan

Order Notes FunctionBlock Macrocell PC44 VQ44 CS48 BScan

Order Notes

1 1 2 40 D6 105 2 1 1 39 D7 511 2 3 41 C7 102 2 2 44 38 E5 481 3 5 43 B7 99 [1] 2 3 42 36 E6 45 [1]1 4 4 42 C6 96 2 4 43 37 E7 421 5 6 44 B6 93 [1] 2 5 40 34 F6 39 [1]1 6 8 2 A6 90 2 6 39 33 G7 36 [1]1 7 7 1 A7 87 [1] 2 7 38 32 G6 331 8 9 3 C5 84 2 8 37 31 F5 301 9 11 5 B5 81 2 9 36 30 G5 271 10 12 6 A4 78 2 10 35 29 F4 241 11 13 7 B4 75 2 11 34 28 G4 21

1 12 14 8 A3 72 2 12 33 27 E3 181 13 18 12 B2 69 2 13 29 23 F2 151 14 19 13 B1 66 2 14 28 22 G1 121 15 20 14 C2 63 2 15 27 21 F1 91 16 22 16 C3 60 2 16 26 20 E2 61 17 24 18 D2 57 2 17 25 19 E1 31 18 – – - 54 2 18 - - - 0

Note: [1] Global control pin Note: [1] Global control pin

Pin Type PC44 VQ44 CS48

I/O/GCK1 5 43 B7I/O/GCK2 6 44 B6I/O/GCK3 7 1 A7I/O/GTS1 42 36 E6I/O/GTS2 40 34 F6I/O/GSR 39 33 G7

TCK 17 11 A1TDI 15 9 B3TDO 30 24 G2TMS 16 10 A2

VCCINT 5 V 21,41 15,35 C1,F7VCCIO 3.3 V/5 V 32 26 G3

GND 23,10,31 17,4,25 A5, D1, F3No Connects — — C4, D3, D4, E4




Component Availability

C = Commercial (0°C to +70°C), I = Industrial (–40°C to +85°C)

Revision Control

Speed Options

-15 15 ns pin-to-pin delay-10 10 ns pin-to-pin delay

-7 7.5 ns pin-to-pin delay-6 6 ns pin-to-pin delay-5 5 ns pin-to-pin delay

Packaging Options

PC44 44-Pin Plastic Leaded Chip Carrier (PLCC)VQ44 44-Pin Thin Quad Pack (VQFP)CS48 48-Pin Chip Scale Package (CSP)

Temperature Options

C = Commercial (0°C to +70°C)I = Industrial (–40°C to +85°C)

XC9536 -5 PC 44 C

Device Type

SpeedPackage Type

Number of Pins

Temperature Range

Pins 44 48

TypePlasticPLCC

PlasticVQFP

PlasticCSP

Code PC44 VQ44 CS48

XC9536

–15 C,I C,I -–10 C,I C,I C–7 C,I C,I C–6 C C -–5 C C C

Date Reason6/3/98 Revise datasheet to reflect new CSP package pinouts & ordering code.

11/2/98 Revise datasheet to reflect new AC characteristics and Internal Timing Parameters.12/04/98 Revise datasheet to remove PCI compliancy statement and remove tLF.


ANEXOS 4 – Lista de Material

ANEXOS 4

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ANEXOS 4 – Lista de Material

ccxviii

Lista do material implementado

Trabalho Nº 1

Descrição do Material Quantidade 7805 1X Díodo 1N4001 4X Resistência de 150 Ω 1X Resistência de 1 KΩ 1X Condensador de 0.01 µF 6X Condensador de 0.1 µF 1X Condensador de 1 µF 3X Condensador de 4.7 µF 2X Condensador de 10 µF 1X Condensador de 33 µF 1X Condensador de 22 pF 1X Condensador de 33 pF 2X Cristal de 11.0592 MHz 1X MAX233 1X MAX1112 1X L293 2X HEF4047 1X AT89C51 1X XC9536 1X Adaptador PLCC44 – DIP40 1X Botão de Pressão 1X Conector DB9 (Porta Série) 1X Cabo porta Série 1X Breadboard 2X Placa PCB 1X Trabalho Nº 2

Descrição do Material Quantidade LDR 2X Fototransistor 1X Potenciómetro de 5 KΩ 2X Díodo 1N4001 1X Resistência de 10 KΩ 2X Resistência de 150 Ω 2X Resistência de 4,7 KΩ 1X Condensador de 0.01 µF 2X GL494 2X L293 1X Breadboard 1X Placa PCB 1X

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