ELC-1103 - Lista 01 Amp shaush dsaij ahsdiua ndj iasjn dasjni saDiff.pdf
3
Ministério da Educação UNIVERSIDADE FEDERAL DE SANTA MARIA - UFSM Departamento de Eletrônica e Computação - DELC 97105-900 – Santa Maria - RS Fone: (0xx.55) 3220 8418 e-mail: [email protected] Dispositivo e Circuitos Eletrônicos III – Lista de Exercícios Amplificadores Diferenciais Aula 1: 1. A bipolar differential pair employs a load resistance (R C ) of 1 k and a tail current (I EE ) of 1 mA. How close to V CC can V CM be chosen? 2. What value of R C allows the input CM level to approach V CC is the transistors can tolerate a base-collector forward bias of 400 mV? 3. A bipolar differential pair employs a tail current (I EE ) of 0.5 mA and a collector resistance (R C ) of 1 k. What is the maximum allowable base voltage if the differential input is large enough to completely steer the tail current? Assume V CC = 2,5 V. 4. Repeat the above exercise if the tail current is raised to 1 mA. 5. Design a bipolar differential pair for a gain of 10 and a power budget of 1 mW with a supply voltage of 2 V. 6. Redesign the circuit for a power budget of 0,5 mW and compare the results. 7. Compare the power dissipation of a bipolar differential pair with that of a Common-Emitter (CE) stage if both circuits are designed for equal voltage gains (AV), collector resistances (RC), and supply voltages (VCC). 8. If both circuits are designed for the same power budget, equal collector resistances, and equal supply voltages, compare their voltage gains. 9. Determine the differential input voltage that steers 98% of the tail current to one transistor. 10. What differential input is necessary to steer 90% of the tail current? 11. Sketch the output waveforms of the bipolar differential pair in Fig. 10.14(a) in response to the sinusoidal inputs shown in Figs. 10.14(b) and (c). Assume Q 1 and Q 2 remain in the forward active region. 12. What happens to the above results (exercise 11) if the tail current is halved? 13. Compute the differential gain of the circuit shown in Fig. 10.16, where ideal current sources are used as loads to maximize the gain.
-
Upload
lucas-prevedello -
Category
Documents
-
view
6 -
download
1
description
saidj asas das sdnas idnsa jdnasi jnd aisjnd aisn daisndi asnd aisndjasn dis aijis and iasjnd iasjndiasjndiasndijasnidjasnid asnd asijdasn dansijdnas iydbasuyd asybdh uasb243 uhb1 uh3b 12uhb dsjadnb quwhb unduqhwnd uy1hb2uhhuqwbd uhsadas
Transcript of ELC-1103 - Lista 01 Amp shaush dsaij ahsdiua ndj iasjn dasjni saDiff.pdf
Ministério da Educação UNIVERSIDADE FEDERAL DE SANTA MARIA - UFSM Departamento de Eletrônica e Computação - DELC
97105-900 – Santa Maria - RS Fone: (0xx.55) 3220 8418 e-mail: [email protected]
Dispositivo e Circuitos Eletrônicos III – Lista de Exercícios
Amplificadores Diferenciais
Aula 1:
1. A bipolar differential pair employs a load resistance (RC) of 1 k and a tail
current (IEE) of 1 mA. How close to VCC can VCM be chosen?
2. What value of RC allows the input CM level to approach VCC is the transistors
can tolerate a base-collector forward bias of 400 mV?
3. A bipolar differential pair employs a tail current (IEE) of 0.5 mA and a collector
resistance (RC) of 1 k. What is the maximum allowable base voltage if the
differential input is large enough to completely steer the tail current? Assume
VCC = 2,5 V.
4. Repeat the above exercise if the tail current is raised to 1 mA.
5. Design a bipolar differential pair for a gain of 10 and a power budget of 1 mW
with a supply voltage of 2 V.
6. Redesign the circuit for a power budget of 0,5 mW and compare the results.
7. Compare the power dissipation of a bipolar differential pair with that of a
Common-Emitter (CE) stage if both circuits are designed for equal voltage gains
(AV), collector resistances (RC), and supply voltages (VCC).
8. If both circuits are designed for the same power budget, equal collector
resistances, and equal supply voltages, compare their voltage gains.
9. Determine the differential input voltage that steers 98% of the tail current to one
transistor.
10. What differential input is necessary to steer 90% of the tail current?
11. Sketch the output waveforms of the bipolar differential pair in Fig. 10.14(a) in
response to the sinusoidal inputs shown in Figs. 10.14(b) and (c). Assume Q1
and Q2 remain in the forward active region.
12. What happens to the above results (exercise 11) if the tail current is halved?
13. Compute the differential gain of the circuit shown in Fig. 10.16, where ideal
current sources are used as loads to maximize the gain.
Fig. 10.16
14. Figure 10.17 illustrates an implementation of the topology shown in Fig. 10.16.
Calculate the differential voltage gain.
Figure 10.17
15. Determine the differential gain of the circuit in Fig. 10.19 if VA< ∞.
Figure 10.19
16. Repeat the above example if R1 ≠ R2.
17. Calculate the differential gain of the circuit illustrated in Fig. 10.20 if VA< ∞.
Figure 10.20
18. Calculate the gain if VA = 4 V for all transistors, R1=R2=10 kΩ , and IEE =1 mA.
19. Determine the gain of the degenerated differential pairs shown in Figs. 10.21(a)
and (b). Assume VA= ∞.
Figure 10.21
20. Design each circuit for a gain of 5 and power consumption of 2 mW. Assume
VCC = 2,5 V, VA = ∞, and RE = 2/gm.
