Tecnologiade* circuitos* lógicosintegradosbassani/EA-772/Aulas/Aula_Tecnologia-João-2018... ·...

Tecnologia de circuitos lógicos integrados João Carlos Mar+ns de Almeida [email protected]

Pontos abordados •  Elementos básicos •  Diodos •  BJTs •  MOSFETs

•  Caracterís+cas principais de CIs

•  Exemplo de projeto de circuito lógico

•  Montagem de um circuito em protoboard

Blocos lógicos

EA-772 Circuitos Lógicos – Aula 12

Primeiro Semestre de 2014, Professor: Bassani, JWM

2

ABRIL DE 2014

Aula 12.

Circuitos e funções booleanas elementares

Blocos lógicos: representações das funções booleanas elementares

a

b

a · b

a

b

a + b a a’

Tabela verdade

Tabela que relaciona todas as combinações das entradas com o valor de saída, que é o

resultado da avaliação de uma função booleana.

F(a,b,c)= a’b c’ + a’bc + ab’c + abc

a b c x

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

a b x

0 0 0

0 1 0

1 0 0

1 1 1

a b x

0 0 0

0 1 1

1 0 1

1 1 1

entradas

saída

22

= 4

23

= 8

Trata-se da

especificação

do circuito a

ser construído

para resolver

um problema

específico!

AND

a b a�b

0 0 0

0 1 0

1 0 0

1 1 1

OR

a b a+b

0 0 0

0 1 1

1 0 1

1 1 1

NOT

a a’

0 1

1 0

Diodos

Diodos! Diodo ideal:

1 4 4 ! CHAPTER 3 D I O D E S

loo n I — w v

ID — = »

OH

•12 V

(a) (b)

FIGURE 3 .4 Circuit and waveforms for Example 3.1.

SOLUTION

The diode conducts when vs exceeds 12 V, as shown in Fig. 3.4(b). The conduction angle is 20, where G is given by

24 cos0 = 12

Thus 9= 60° and the conduction angle is 120°, or one-third of a cycle. The peak value of the diode current is given by

Id = 2Jiw = 0-12A

The maximum reverse voltage across the diode occurs when vs is at its negative peak and is equal to 24 + 12 = 36 V.

3.1.3 Another Application: Diode Logic Gates Diodes together with resistors can be used to implement digital logic functions. Figure 3.5 shows two diode logic gates. T o see h o w these circuits function, consider a posi t ive-logic system in which vol tage values close to 0 V correspond to logic 0 (or low) and voltage values

VA o-

VBo-

VC o-

-W-

-W-

R

(a)

- O VY

vco-

-KH

-W-

-W-

+ 5 V A

R

(b)

FIGURE 3 . 5 Diode logic gates: (a) OR gate; (b) AND gate (in a positive-logic system).

3.1 T H E I D E A L D I O D E . 1 4 5

close to +5 V correspond to logic 1 (or h igh) . The circuit in Fig. 3.5(a) has three inputs, vA, vB and vc. It is easy to see that diodes connected to +5-V inputs will conduct , thus c lamping the output vY to a va lue equal to +5 V. This posi t ive vol tage at the output will keep the diodes whose inputs are low (around 0 V) cut off. Thus the output will b e h igh if one or more of the inputs are high. The circuit therefore implements the logic O R function, which in Boolean notat ion is expressed as

Y=A+B+C

Similarly* the reader is encouraged to show that us ing the same logic sys tem ment ioned above, the circuit of Fig. 3.5(b) implements the logic A N D function,

Y = A B C

4 m

• M m

I'M

BS

Assuming the diodes to be ideal, find the values of / a n d Vin the circuits of Fig. 3.6.

D ,5Z I '

•5 kn

•10 V

+ 10 V A

(a)

+ 10 V A

i o k a

D2

tZD2 D T I J 7

io k n

t • io v

5 k n

¿52 I ' '

tLD2

(b)

FIGURE 3.6 Circuits for Example 3.2.

Solution In these circuits it might not be obvious at first sight whether none, one, or both diodes are con-ducting. In such a case, we make a plausible assumption, proceed with the analysis, and then check whether we end up with a consistent solution. For the circuit in Fig. 3.6(a), we shall assume that both diodes are conducting. It follows that VB = 0 and V = 0. The current through D2 can now be determined from

ID2 — 1 0 - 0

10 1 m A

D1

D2

VA VB D1 D2 Vγ

0 +V cortado cortado 0

0 +V cortado conduz +V

+V 0 conduz cortado +V

+V +V conduz conduz +V

γ = A + B

1 4 4 ! CHAPTER 3 D I O D E S

loo n I — w v

ID — = »

OH

•12 V

(a) (b)

FIGURE 3 .4 Circuit and waveforms for Example 3.1.

SOLUTION

The diode conducts when vs exceeds 12 V, as shown in Fig. 3.4(b). The conduction angle is 20, where G is given by

24 cos0 = 12

Thus 9= 60° and the conduction angle is 120°, or one-third of a cycle. The peak value of the diode current is given by

Id = 2Jiw = 0-12A

The maximum reverse voltage across the diode occurs when vs is at its negative peak and is equal to 24 + 12 = 36 V.

3.1.3 Another Application: Diode Logic Gates Diodes together with resistors can be used to implement digital logic functions. Figure 3.5 shows two diode logic gates. T o see h o w these circuits function, consider a posi t ive-logic system in which vol tage values close to 0 V correspond to logic 0 (or low) and voltage values

VA o-

VBo-

VC o-

-W-

-W-

R

(a)

- O VY

vco-

-KH

-W-

-W-

+ 5 V A

R

(b)

FIGURE 3 . 5 Diode logic gates: (a) OR gate; (b) AND gate (in a positive-logic system).

3.1 T H E I D E A L D I O D E . 1 4 5

close to +5 V correspond to logic 1 (or h igh) . The circuit in Fig. 3.5(a) has three inputs, vA, vB and vc. It is easy to see that diodes connected to +5-V inputs will conduct , thus c lamping the output vY to a va lue equal to +5 V. This posi t ive vol tage at the output will keep the diodes whose inputs are low (around 0 V) cut off. Thus the output will b e h igh if one or more of the inputs are high. The circuit therefore implements the logic O R function, which in Boolean notat ion is expressed as

Y=A+B+C

Similarly* the reader is encouraged to show that us ing the same logic sys tem ment ioned above, the circuit of Fig. 3.5(b) implements the logic A N D function,

Y = A B C

4 m

• M m

I'M

BS

Assuming the diodes to be ideal, find the values of / a n d Vin the circuits of Fig. 3.6.

D ,5Z I '

•5 kn

•10 V

+ 10 V A

(a)

+ 10 V A

i o k a

D2

tZD2 D T I J 7

io k n

t • io v

5 k n

¿52 I ' '

tLD2

(b)

FIGURE 3.6 Circuits for Example 3.2.

Solution In these circuits it might not be obvious at first sight whether none, one, or both diodes are con-ducting. In such a case, we make a plausible assumption, proceed with the analysis, and then check whether we end up with a consistent solution. For the circuit in Fig. 3.6(a), we shall assume that both diodes are conducting. It follows that VB = 0 and V = 0. The current through D2 can now be determined from

ID2 — 1 0 - 0

10 1 m A

D1

D2

VA VB D1 D2 Vγ

0 0 conduz conduz 0

0 +V conduz cortado 0

+V 0 cortado conduz 0

+V +V cortado cortado +5V

γ = AB

9 0 t\. CHAPTER 3 D I O D E S

reaches -2Vp. In response to this waveform, the peak-detector section provides across capacitor C 2 a negat ive dc vol tage of magni tude 2Vp. Because the output vol tage is double the input peak, the circuit is k n o w n as a vol tage doubler . T h e technique can be extended to provide output dc vol tages that are higher mult iples of Vp.

3.28 If the diode in the circuit of Fig. 3.36 is reversed, what will the dc component of v„ become? Ans. - 5 V

S 3.7 PHYSICAL OPERATION OF DIODES

Having studied the terminal characterist ics and circuit applicat ions of junc t ion diodes , w e will n o w briefly consider the physica l processes that give r ise to the observed terminal char-acteristics. The fol lowing t reatment of device phys ics is somewha t simplified; never theless , it should provide sufficient background for a fuller unders tanding of diodes and for under-standing the operat ion of transistors in the fol lowing t w o chapters .

3.7.1 Basic Semiconductor Concepts

The pn Junction The semiconductor diode is basically a p n junct ion, as shown schemati-cally in Fig. 3.39. As indicated, the pn junct ion consists of p - type semiconductor mater ial (e.g., s i l icon) b rough t into c lose contact wi th n-typc semiconductor mater ia l (also sil icon). In actual pract ice, both the p and n regions are part of the same silicon crystal ; that is, the pn junc t ion is formed within a single silicon crystal by creat ing regions of different "dop ings " (p and n regions) . Append ix A provides a brief descript ion of the process e m p l o y e d in the fabrication of pn junct ions . A s indicated in Fig. 3.39, external wi re connect ions to the p and n reg ions (i.e., d iode terminals) are m a d e through meta l ( a luminum) contacts .

In addit ion to being essentially a diode, the pn j unc t ion is the basic e lement of bipolar junc t ion transistors (BJTs) and p lays an impor tan t ro le in t he operat ion of field-effect t ran-sistors (FETs) . Thus an unders tanding of the physica l operat ion of junc t ions is important to the understanding of the operation and terminal characteristics both of diodes and transistors.

Intrinsic Silicon Although either silicon or ge rmanium can b e used to manufacture semi-conductor devices—indeed, earlier diodes and transistors were m a d e of germanium-—today's

Metal contact Metal contact

Anode

/ '-[> Pe •

s i l i c o n MÜCOII Cathode

FIGURE 3 . 3 9 Simplified physical structure of the junction diode. (Actual geometries are given in Appendix A.)

3.7 P H Y S I C A L O P E R A T I O N O F D I O D E S

Valence Covalent electrons bonds

Silicon atoms

FIGURE 3 .40 Two-dimensional representation of the silicon crystal. The circles represent the inner core of silicon atoms, with +4 indicating its positive charge of +4q, which is neutralized by the charge of the four valence electrons. Observe how the covalent bonds are formed by sharing of the valence electrons. At 0 K, all bonds are intact and no free electrons are available for current conduction.

integrated-circuit technology is based almost entirely on silicon. For this reason, w e will deal mostly with silicon devices throughout this b o o k . 6

A crystal of pure or intrinsic silicon has a regular lattice structure where the a toms are held in their posi t ions by bonds , called covalent bonds , formed by the four valence elec-trons associated with each silicon atom. Figure 3.40 shows a two-dimensional representa-tion of such a structure. Observe that each a tom shares each of its four valence electrons with a neighbor ing atom, with each pair of electrons forming a covalent bond. A t suffi-ciently low temperatures , all covalent bonds are intact and no (or very few) free e lectrons are available to conduct electric current. However , at r o o m temperature, some of the bonds are broken by thermal ionization and some electrons are freed. As shown in Fig. 3 .41 , when a covalent bond is broken, an electron leaves its parent a tom; thus a posi t ive charge, equal to the magni tude of the electron charge, is left with the parent a tom. A n electron from a neigh-boring a tom m a y b e attracted to this posi t ive charge, leaving its parent a tom. This action fills up the "ho le " that existed in the ionized a tom but creates a n e w hole in the other a tom. This process m a y repeat itself, wi th the result that w e effectively have a posit ively charged carrier, or hole , mov ing through the silicon crystal structure and being available to conduct electric current. The charge of a hole is equal in magni tude to the charge of an electron.

Thermal ionization results in free electrons and holes in equal numbers and hence equal concentrations. These free electrons and holes m o v e randomly through the silicon crystal structure, and in the process some electrons may fill some of the holes. This process, called recombination, results in the disappearance of free electrons and holes . The recombinat ion rate is proport ional to the number of free electrons and holes , which, in turn, is determined by

6 An exception is the subject of gallium arsenide (GaAs) circuits, which though not covered in this edition of the book, is studied in some detail in material provided on the text website and on the CD accompanying the text.

Operação 9ísica do diodo

1 9 2 „ . C H A P T E R S D I O D E S

the ionization rate. The ionization rate is a strong function of temperature. In thermal equilib-r ium, the recombinat ion rate is equal to the ionization or thermal-generat ion rate, and one can calculate the concentration of free electrons n, which is equal to the concentrat ion of holes p,

n = p = nt

where nt denotes the concentrat ion of free electrons or holes in intrinsic silicon at a given temperature . Study of semiconductor physics shows that at an absolute temperature T (in kelvins) , the intrinsic concentrat ion (i.e., the number of free electrons and holes per cubic cent imeter) can be found from

rij = BT e (3 .36)

where B is a mater ia l -dependent parameter = 5.4 x 1 0 3 1 for silicon, EG is a parameter k n o w n as the bandgap energy = 1 . 1 2 electron volts (eV) for silicon, and k is Bo l t zmann ' s constant = 8.62 x 1 0 - 5 eV/K. Al though w e shall not m a k e use of the bandgap energy in this circuit-focused introductory exposit ion, it is interest ing to note that EG represents the m i n i m u m energy required to b reak a covalent b o n d and thus genera te an electron-hole pair. Substi tu-tion in Eq . (3.36) of the parameter values g iven shows that for intrinsic sil icon at r o o m tem-perature (T ~ 300 K) , nt = 1.5 x 1 0 1 U carr iers /cnv\ T o p lace this n u m b er in perspect ive, w e

99 o

note that the silicon crystal has about 5 x 1 0 a toms /cm . Thus , at r o o m temperature , only one of every billion a toms is ionized!

Finally, it should be ment ioned that the reason that silicon is called a s emiconductor is that its conductivi ty, which is determined by the number of charge carriers available to con-duct electric current, is be tween that of conductors (e.g., metals) and that of insulators (e.g., glass).

Diffusion and Drift There are two mechan i sms by which holes and electrons m o v e through a sil icon crystal—diffusion and drift. Diffusion is associated with r a n d o m mot ion due to thermal agitation. In a p iece of sil icon wi th uni form concentrat ions of free electrons

3 . 7 P H Y S I C A L O P E R A T I O N O F D I O D E S Ï :l 1 9 3

u

c

'S

FIGURE 3 .42 A bar of intrinsic silicon (a) in which the hole concentration profile shown in (b) has been created along the x-axis by some unspecified mechanism.

and holes, this r andom mot ion does not result in a net flow of charge (i.e., current). O n the other hand, if by some mechan i sm the concentrat ion of, say, free electrons is m a d e higher in one part of the p iece of si l icon than in another, then electrons will diffuse from the region of high concentration to the region of low concentrat ion. This diffusion process gives rise to a net flow of charge, or diffusion current . As an example , consider the bar of silicon shown in Fig. 3.42(a), in which the hole concentrat ion profile shown in Fig. 3.42(b) has been created along the jc-axis by some unspecified mechanism. The exis tence of such a concentra-tion profile results in a hole diffusion current in the x direction, wi th the magni tude of the current at any point be ing proport ional to the s lope of the concentrat ion curve, or the con-centration gradient, at that point,

Jp = -qDp& (3.37)

where / is the current densi ty (i.e., the current per unit area of the p lane perpendicular to the

9 — 1 9 '

x axis) in A / c m , q is the magni tude of electron charge = 1.6 x 10 C, and Dp is a constant called the diffusion constant or diffusivity of holes . No te that the gradient (dp/dx) is neg-ative, resulting in a posi t ive current in the x direction, as should b e expected. In the case of electron diffusion resul t ing from an electron concentra t ion gradient, a s imilar re lat ionship applies, giving the electron-current density

Jn = qDn^ (3.38)

where Dn is the diffusivity of electrons. Observe that a negat ive (dn/dx) gives rise to a neg-ative current, a result of the convent ion that the posi t ive direction of current is taken to b e that of the flow of posi t ive charge (and opposi te to that of the flow of negat ive charge). For holes and electrons diffusing in intrinsic silicon, typical values for the diffusion constants are Dp=l2 c m 2 / s and Dn = 34 c m 2 / s .

The other m e c h a n i s m for carrier mot ion in semiconductors is drift. Carrier drift occurs when an electric field is applied across a piece of silicon. Free electrons and holes are accelerated by the electric field and acquire a velocity componen t (super imposed on the velocity of their thermal mot ion) called drift velocity. If the electric field strength is denoted

1 9 4 CHAPTER 3 D I O D E S

E (in V/cm) , the posit ively charged holes will drift in the direction of E and acquire a

velocity vdrifi (in cm/s) given by

vdrift = VPE (3.39)

where ^ is a constant called the mobil ity of holes which has the units of c m 2 / V - s . For intrin-sic silicon, fip is typically 480 c m 2 / V - s . The negatively charged electrons will drift in a

direction opposite to that of the electric field, and their velocity is given by a relationship sim-ilar to that in Eq. (3.39), except that /ip is replaced by //„, the electron mobil i ty . For intrinsic silicon, p:n is typically 1350 c m 2 / V - s , about 2.5 t imes greater than the hole mobil i ty.

Consider n o w a silicon crystal having a hole density p and a free-electron density n sub-jec ted to an electric field E. The holes will drift in the same direction as E (call it the x direc-tion) with a velocity fipE. Thus we have a posi t ive charge of density qp (coulomb/cm 3 ) mov ing in the x direction with velocity j^E (cm/s) . It fol lows that in 1 second, a charge of qpHpEA (coulomb) will cross a p lane of area A ( c m 2 ) perpendicular to the x-axis. This is the current componen t caused by hole drift. Div id ing by the area A gives the current density

J

P-drift = qPHpE (3.40a)

T h e free electrons will drift in the direction opposi te to that of E. Thus we have a charge of density (-qn) mov ing in the negat ive x direction, and thus it has a negat ive velocity (-/J^E). T h e result is a posi t ive current componen t wi th a density given by

J n-drift = qny,nE (3.40b)

The total drift current density is obtained by combin ing Eqs . (3.40a) and (3.40b),

J drift = q{pilp + nnn)E (3.40c)

It should b e noted that this is a form of O h m ' s law with the resistivity p (in units of Q- cm) given by

p = l/lq(pflp + nfi„)] (3.41)

Finally, it is wor th ment ioning that a s imple relat ionship, k n o w n as the Einste in rela-t ionship, exists be tween the carrier diffusivity and mobil i ty,

5R! = 2P = V . (3.42)

where V r is the thermal voltage that w e have encountered before, in the diode i-v relationship (see Eq . 3.1). Recal l that at r o o m temperature , VT = 25 m V . The reader can easily check the validity of Eq . (3.42) by substi tuting the typical values given above for intrinsic silicon.

DOPED SEMICONDUCTORS The intrinsic sil icon crystal described above has equal con-centrat ions of free electrons and holes generated by thermal ionization. These concentra-t ions, denoted are strongly dependent on temperature . Doped semiconductors are materials in which carriers of one k ind (electrons or holes) predominate . Doped silicon in which the majori ty of charge carriers are the negatively charged electrons is called n type, while sil icon doped so that the majority of charge carriers are the positively charged holes is called p type.

Doping of a silicon crystal to turn it into n type or p type is achieved by introducing a small numbe r of impuri ty a toms. For instance, introducing impuri ty atoms of a pentavalent e lement such as phosphorus results in n-type silicon, because the phosphorus atoms that replace some of the silicon a toms in the crystal structure have five valence electrons, four of

3.7 P H Y S I C A L O P E R A T I O N O F D I O D E S T"\L 1 9 5

which form bonds with the neighbor ing silicon a toms whi le the fifth become s a free electron (Fig. 3.43). Thus each phosphorus a tom donates a free electron to the silicon crystal, and the phosphorus impuri ty is called a donor . It should be clear, though, that no holes are gener-ated by this process; hence the majority of charge carriers in the phosphorus-doped silicon will be electrons. In fact, if the concentrat ion of donor a toms (phosphorus) is ND, in thermal equilibrium the concentrat ion of free electrons in the n- type silicon, nn0, wil l be

nn0 - ND (3.43)

where the additional subscript 0 denotes thermal equil ibrium. F r o m semiconductor physics , it turns out that in thermal equi l ibr ium the product of electron and hole concentrat ions remains constant; that is,

nnoPno = A (3.44)

Thus the concentrat ion of holes , pn0, that are generated by thermal ionizat ion will be

2 H i (3.45)

Pn0~TTD

Since rii is a function of temperature (Eq. 3.36), it follows that the concentrat ion of the minority holes will b e a function of temperature whereas that of the majori ty electrons is independent of temperature .

To produce a p-type semiconductor , silicon has to b e doped wi th a tr ivalent impuri ty such as boron. Each of the impuri ty boron a toms accepts one electron from the silicon crys-tal, so that they m a y form covalent bonds in the lattice structure. Thus , as shown in Fig. 3.44, each boron a tom gives rise to a hole , and the concentrat ion of the majority holes in p-type silicon, under thermal equil ibr ium, is approximately equal to the concentrat ion NA of the acceptor (boron) impuri ty ,

PPo = NA

(3.46)

Fisicamente:

1 9 6 . . . CHAPTER 3 D |ODES

Valence electrons

Covalent bonds

Silicon atom

Trivalent impurity atom (acceptor)

Hole

FIGURE 3 .4 4 A silicon crystal doped with a trivalent impurity. Each dopant atom gives rise to a hole, and the semiconductor becomes p type.

In this / H y p e silicon, the concentrat ion of the minor i ty electrons, which are generated by thermal ionization, can be calculated using the fact that the product of carrier concentrat ions remains constant; thus,

np0 - I (3.47)

It should be emphasized that a piece of n-type or / H y p e silicon is electrically neutral; the majority free carriers (electrons in n-type silicon and holes in / H y p e silicon) are neutralized by b o u n d c h a r g e s associated with the impuri ty a toms.

EXERCISES

3.29 Calculate the intrinsic carrier density ?z; at 250 K. 300 K. and 350 K.

Ans. 1.5 x 10 8 /cm 3 ; 1.5 x 10 , ( , /cin3: 4.18 x 101 ' / cm 3

3.30 Consider an n-type silicon in which the dopant concentration ND is lO'Vcnr. Find the electron and hole concentrations at 250 K, 300 K, and 350 K. You may use the results of Exercise 3.29. Ans. I () 1 7 , 2.25 x 10 "'; 1() ) 7 , 2.25 x 10 3 ; 1 0 1 7 , 1.75 x 10f' (all per cm 3 )

3.31 Find (he resistivity of (a) intrinsic silicon and (b)/>-lypc silicon with NA = 10 l 6 / cm 3 . Use «, = 1.5 x 10 Vein-1, and assume that lor intrinsic silicon u„ = 1 3 5 0 cm 2 /V-s and f.ip = 480 cni 2 /V-s and for the doped silicon ,u„ = 1110 cm 2 /V-s and ,up = 400 cm 2 /V-s . (Note that doping results in reduced carrier mobilities.) Ans. (a)2.28 x 10 5 £2-cm ; (b) 1.5612-cm

3.7.2 The p n Junction Under Open-Circuit Conditions Figure 3.45 shows a pn junct ion under open-circui t condi t ions—that is, the external termi-nals are left open. The " + " signs in the / H y p e mater ia l denote the majority holes . T h e charge

3.7 PHYSICAL O P E R A T I O N OF D IODES

Bound charges

Holes + 4 - 4 - 4 + + + + M

O o Free electron-.

+ P + H + + + H + + + J -

.«fr-o o

• • • •

Depletion region

(a)

x

(b)

FIGURE 3 .45 (a) The pn junction with no applied voltage (open-circuited terminals), (b) The potential distribution along an axis perpendicular to the junction.

of these holes is neutral ized by an equal amount of bound negat ive charge associated with the acceptor a toms. For simplicity, these bound charges are not shown in the diagram. Also not shown are the minor i ty electrons generated in the / H y p e mater ia l by thermal ionization.

In the w-type mater ia l the majority electrons are indicated by " - " signs. Here also, the bound posit ive charge, wh ich neutralizes the charge of the majority electrons, is not shown in order to keep the d iagram simple. The n- type material also contains minori ty holes gener-ated by thermal ionizat ion that are not shown in the diagram.

The Di f fus ion C u r r e n t lD Because the concentrat ion of holes is h igh in the p region and low in the n region, holes diffuse across the junct ion from the p side to the n side; similarly, electrons diffuse across the junct ion from the n side to the p side. These two current c o m p o-nents add together to form the diffusion current I D , whose direction is from the p s ide to the n side, as indicated in Fig. 3.45.

The D e p l e t i o n R e g i o n The holes that diffuse across the junc t ion into the n region quickly recombine wi th some of the majority electrons present there and thus disappear from the scene. This recombinat ion process results in the disappearance of some free elec-trons from the n- type mater ial . Thus some of the bound posi t ive charge will no longer be neutralized by free electrons, and this charge is said to have been u n c o v e r e d . Since recom-bination takes p lace close to the junct ion , there will be a region close to the junct ion that is depleted of free electrons and contains uncovered bound posi t ive charge, as indicated in Fig. 3.45.

1 9 6 . . . CHAPTER 3 D |ODES

Valence electrons

Covalent bonds

Silicon atom

Trivalent impurity atom (acceptor)

Hole

FIGURE 3 .4 4 A silicon crystal doped with a trivalent impurity. Each dopant atom gives rise to a hole, and the semiconductor becomes p type.

In this / H y p e silicon, the concentrat ion of the minor i ty electrons, which are generated by thermal ionization, can be calculated using the fact that the product of carrier concentrat ions remains constant; thus,

np0 - I (3.47)

It should be emphasized that a piece of n-type or / H y p e silicon is electrically neutral; the majority free carriers (electrons in n-type silicon and holes in / H y p e silicon) are neutralized by b o u n d c h a r g e s associated with the impuri ty a toms.

EXERCISES

3.29 Calculate the intrinsic carrier density ?z; at 250 K. 300 K. and 350 K.

Ans. 1.5 x 10 8 /cm 3 ; 1.5 x 10 , ( , /cin3: 4.18 x 101 ' / cm 3

3.30 Consider an n-type silicon in which the dopant concentration ND is lO'Vcnr. Find the electron and hole concentrations at 250 K, 300 K, and 350 K. You may use the results of Exercise 3.29. Ans. I () 1 7 , 2.25 x 10 "'; 1() ) 7 , 2.25 x 10 3 ; 1 0 1 7 , 1.75 x 10f' (all per cm 3 )

3.31 Find (he resistivity of (a) intrinsic silicon and (b)/>-lypc silicon with NA = 10 l 6 / cm 3 . Use «, = 1.5 x 10 Vein-1, and assume that lor intrinsic silicon u„ = 1 3 5 0 cm 2 /V-s and f.ip = 480 cni 2 /V-s and for the doped silicon ,u„ = 1110 cm 2 /V-s and ,up = 400 cm 2 /V-s . (Note that doping results in reduced carrier mobilities.) Ans. (a)2.28 x 10 5 £2-cm ; (b) 1.5612-cm

3.7.2 The p n Junction Under Open-Circuit Conditions Figure 3.45 shows a pn junct ion under open-circui t condi t ions—that is, the external termi-nals are left open. The " + " signs in the / H y p e mater ia l denote the majority holes . T h e charge

3.7 PHYSICAL O P E R A T I O N OF D IODES

Bound charges

Holes + 4 - 4 - 4 + + + + M

O o Free electron-.

+ P + H + + + H + + + J -

.«fr-o o

• • • •

Depletion region

(a)

x

(b)

FIGURE 3 .45 (a) The pn junction with no applied voltage (open-circuited terminals), (b) The potential distribution along an axis perpendicular to the junction.

of these holes is neutral ized by an equal amount of bound negat ive charge associated with the acceptor a toms. For simplicity, these bound charges are not shown in the diagram. Also not shown are the minor i ty electrons generated in the / H y p e mater ia l by thermal ionization.

In the w-type mater ia l the majority electrons are indicated by " - " signs. Here also, the bound posit ive charge, wh ich neutralizes the charge of the majority electrons, is not shown in order to keep the d iagram simple. The n- type material also contains minori ty holes gener-ated by thermal ionizat ion that are not shown in the diagram.

The Di f fus ion C u r r e n t lD Because the concentrat ion of holes is h igh in the p region and low in the n region, holes diffuse across the junct ion from the p side to the n side; similarly, electrons diffuse across the junct ion from the n side to the p side. These two current c o m p o-nents add together to form the diffusion current I D , whose direction is from the p s ide to the n side, as indicated in Fig. 3.45.

The D e p l e t i o n R e g i o n The holes that diffuse across the junc t ion into the n region quickly recombine wi th some of the majority electrons present there and thus disappear from the scene. This recombinat ion process results in the disappearance of some free elec-trons from the n- type mater ial . Thus some of the bound posi t ive charge will no longer be neutralized by free electrons, and this charge is said to have been u n c o v e r e d . Since recom-bination takes p lace close to the junct ion , there will be a region close to the junct ion that is depleted of free electrons and contains uncovered bound posi t ive charge, as indicated in Fig. 3.45.

+V

+ |

! Prática: transistores

Chave fechada: polarização para que o transistor trabalhe na região de saturação Chave aberta: região de corte

Transistor

Transistores •  BJTs (Bipolar junc+on transistor) – Transistores de junção bipolar: NPN, PNP

•  MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) – Transistores de efeito de campo: Tipo N, +po P

Transistor Bipolar (BJT)Transistor Bipolar (BJT)

Operação 9ísica do BJT

E

C B

E

C B

Modo Junção Emissor-‐Base Junção Coletor-‐Base

Corte Reverso Reverso

A+vo Direto Reverso

A+vo reverso Reverso Direto

Saturação Direto Direto

Estrutura do BJTEstrutura do BJT

Transistor MOSFET 9 5 6 CHAPTER 10 D I G I T A L C M O S L O G I C C I R C U I T S

V[ o -

A

-o %

(a) (b)

FIGURE 10 .4 (a) The CMOS inverter and (b) its representation as a pair of switches oper-ated in a complementary fashion.

to its body , thus el iminating the body effect. Usual ly , the threshold voltages Vtn and Vtp are equal in magni tude; that is, Vtn = \Vtp\ = Vt, which is in the range of 0.2 V to 1 V, with val-ues near the lower end of this range for m o d e r n process technologies having small feature size (e.g., wi th channel length of 0.5 to 0.1 pm or less).

The inverter circuit can be represented by a pair of switches operated in a complementary fashion, as shown in Fig. 10.4(b). As indicated, each switch is modeled by a finite on resistance, which is the source-drain resistance of the respective transistor, evaluated near j vDS\ = 0,

'DSN

'DSP

= 1/

= 1/

(vDD-vt)

(VDD-Vt)

(10.6)

(10.7)

V 0 i = 0, and the output node

D S N of the pul l -down transistor QN. Thus, in

10.2.2 Static Operation With vj = 0,vo = V0H = VDD, and the output node is connected to VDD through the resistance rDSp of the pul l-up transistor QP. Similarly, with v, = VDD, v0

is connected to ground through the resistance r, the steady state, no direct-current path exists be tween VDD and ground, and the static-current and the stat ic-power dissipation are both zero ( leakage effects are usually negligibly small part icularly for large-feature-size devices) .

The vol tage transfer characteristic of the inverter is shown in Fig. 10.5, from which it is confi rmed that the output vol tage levels are 0 and VDD, and thus the output vol tage swing is the m a x i m u m possible . The fact that V0L and V0H are independent of device dimensions makes C M O S very different from other forms of M O S logic.

T h e C M O S inverter can b e m a d e to switch at the midpoin t of the logic swing, 0 to VDD, that is , at VDD/2, by appropriately sizing the transistors. Specifically, it can b e shown that the switching threshold Vth (or VM) is given by

V, \v,P\ +JkykPvtn

1 + Jkn/k (10.8)

where kn = k'„(W/L)n and kp = k'p(W/L)p, from which w e see that for the typical case where

V,n = \Vtp\, Vth = VDD/2 for kn = *„, that is,

k'n(W/L)„ = k'p(W/L)p (10.9)

10.2 D E S I G N A N D P E R F O R M A N C E A N A L Y S I S O F T H E C M O S I N V E R T E R

Slope = - 1

FIGURE 10 .5 The voltage transfer charac-teristic (VTC) of the CMOS inverter when QN

and QP are matched.

Thus a symmetr ica l transfer characteristic is obtained when the devices are designed to have equal t ransconductance parameters , a condit ion w e refer to as matching. Since pn is two to four t imes larger than pp, matching is achieved by making (W/L) two to four t imes (i.e., pn/pp t imes) (W/L)n,

?! - ?,(!). Normal ly , the two devices have the same channel length, L, which is set at the m i n i m u m allowable for the given process technology. The m i n i m u m width of the N M O S transistor is usually one and a half to two t imes L, and the width of the P M O S transistor two to three times that. For example, for a 0 .25-^m process for which pn/pp =3,L = 0.25 pm, (W/L)„ = 0.375 J U M / 0 . 2 5 pm, and (W/L)p = 1.125 / i m / 0 . 2 5 pm. As we shall discuss shortly, if the inverter is required to drive a relatively large capacit ive load, the transistors are m a d e wider. However , to conserve chip area, mos t of the inverters would have this " M I N I M U M size ." For future purposes , we shall denote the (W/L) ratio of the N M O S transistor of this m in imum-size inverter by n and the (W/L) ratio of the P M O S transistor by p. Since the inverter area can be represented by WnLn + WpLp = (W„ + WP)L, the area of the min imum-s ize inverter is (n + p)L , and we can use the factor (n + p) as a proxy for area. For the example cited earlier, n=\.5,p = 4 .5 , and the area factor n +p = 6.

Besides placing the gate threshold at the center of the logic swing, match ing the transconductance parameters of QN and QP provides the inverter wi th equal current-driving capability in both directions (pull-up and pul l -down) . Fur thermore , and obviously related, it makes rDSN = rDSP. Thus an inverter with matched transistors will have equal propagat ion delays, tPLH and tPHL.

When the inverter threshold is at VDD/2, the noise margins NMH and NML are equalized, and their values are maximized, such that (Section 4.10):

NMH=NML = \(VDD + \Vt) (10.11)

NOT

CHAPTER 1 0 D I G I T A L C M O S LOGIC CIRCUITS

v DD

A o -

B o -C o -

PuJl-up network

-o Y

Ao-

B o -C o -

Pull-doVW: l\H''"ik (P l )N)

FIGURE 1 0 . 8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.

appear at the output, vY = 0. Simul taneously, the P U N will b e off, and no direct dc path will exist be tween VDD and ground. O n the other hand, all input combinat ions that call for a high output (Y= 1) will cause the P U N to conduct , and the P U N will then pull the output node up to VDD, estabhshing an output voltage vY = VDD. Simultaneously, tire P D N will be cut off, and again, no dc current path be tween VDD and ground will exist in the circuit.

N o w , since the P D N comprises N M O S transistors, and since an N M O S transistor conducts when the signal at its gate is high, the P D N is activated (i.e., conducts) when the inputs are high. In a dual manner, the P U N comprises P M O S transistors, and a P M O S transistor conducts when the input signal at its gate is low; thus the P U N is activated when the inputs are low.

The P D N and the P U N each utilizes devices in parallel to form an O R function, and devices in series to form an A N D function. Here , the O R and A N D notation refer to current flow or conduction. Figure 10.9 shows examples of PDNs . For the circuit in Fig. 10.9(a), we observe that QA will conduct when A is high (vA = VDD) and will then pull the output node down to ground (vY = 0 V, Y = 0). Similarly, QB conducts and pulls Y down when B is high. Thus Y

A o—I

-OY

QA BO—\

A o—I

B o—I

-oY

QA

QB A o H QA

-o Y

BO—\\ZQB

C c — j ^ T ß c

F = A + 5 Y = AB

(a) (b)

FIGURE 1 0 . 9 Examples of pull-down networks.

Y = A+BC

(c)

10.3 C M O S LOGIC-GATE CIRCUÍ

A c— j QA B O—I QB

-o Y

Y = A + B y = AB

(a) " (b)

FIGURE 1 0 . 1 0 Examples of pull-up networks.

o Y

B ^-Í\_ZQB

C ( > H | Í I O C

o Y

will be low when A is high or B is high, which can be expressed as

Y = A+B

or equivalently

Y = A + B

The P D N in Fig. 10.9(b) will conduct only when A and B are both high s imultaneously. Thus F w i l l be low when A is h igh and Bis h igh,

or equivalently

Y = AB

Y = AB

As a final example , the P D N in Fig. 10.9(c) will conduct and cause Y to be 0 when A is h igh or when B and C are both high, thus

Y=A+BC

or equivalently

Y=A+BC

Next consider the P U N examples shown in Fig. 10.10. The P U N in Fig. 10.10(a) will conduct and pull Y up to VDD(Y = 1) when A is low or B is low, thus

Y = A + B

The P U N in Fig. 10.10(b) will conduct and produce a h igh output (vY = VDD, Y= 1) only when A and B are both low, thus

Y = AB

Finally, the P U N in Fig. 10.10(c) will conduct and cause Y to be high (logic 1) if A is low if B and C are both low, thus

or

Y=A+BC

Having developed an understanding and an appreciation of the structure and operation of PDNs and P U N s , we now consider complete C M O S gates. Before doing so, however, we wish to introduce alternative circuit symbols, that are almost universally used for M O S transistors by


v DD

A o -

B o -C o -

PuJl-up network

-o Y

Ao-

B o -C o -






A o—I

-OY

QA BO—\

A o—I

B o—I

-oY

QA

QB A o H QA

-o Y

BO—\\ZQB

C c — j ^ T ß c

F = A + 5 Y = AB

(a) (b)


Y = A+BC

(c)



-o Y

Y = A + B y = AB

(a) " (b)


o Y

B ^-Í\_ZQB

C ( > H | Í I O C

o Y


Y = A+B

or equivalently

Y = A + B


or equivalently

Y = AB

Y = AB


Y=A+BC

or equivalently

Y=A+BC


Y = A + B


Y = AB


or

Y=A+BC



v DD

A o -

B o -C o -

PuJl-up network

-o Y

Ao-

B o -C o -






A o—I

-OY

QA BO—\

A o—I

B o—I

-oY

QA

QB A o H QA

-o Y

BO—\\ZQB

C c — j ^ T ß c

F = A + 5 Y = AB

(a) (b)


Y = A+BC

(c)



-o Y

Y = A + B y = AB

(a) " (b)


o Y

B ^-Í\_ZQB

C ( > H | Í I O C

o Y


Y = A+B

or equivalently

Y = A + B


or equivalently

Y = AB

Y = AB


Y=A+BC

or equivalently

Y=A+BC


Y = A + B


Y = AB


or

Y=A+BC


9 6 6 i CHAPTER 10 D I G I T A L C M O S L O G I C C I R C U I T S

o 1 o 1 O c|

NMOS PMOS

(a) (b)

FIGURE 10 .11 Usual and alternative circuit symbols for MOSFETs.

digital-circuit designers. Figure 10.11 shows our usual symbols (left) and the corresponding "digi tal" symbols (right). Observe that the symbol for the P M O S transistor with a circle at the gate terminal is intended to indicate that the signal at the gate has to b e low for the device to be activated (i.e., to conduct) . Thus , in terms of logic-circuit terminology, the gate terminal of the P M O S transistor is an active low input. Besides indicating this property of P M O S devices, the digital symbols omit any indication of which of the device terminals is the source and which is the drain. This should, cause no difficulty at this stage of our study; simply r emember that for an N M O S transistor, the drain is the terminal that is at the higher voltage (current flows from drain to source), and for a P M O S transistor the source is the terminal that is at the higher voltage (current flows from source to drain). To be consistent with the litera-ture, w e shall henceforth use these modified symbols for M O S transistors in logic applica-tions, except in locations where our usual symbols help in understanding circuit operation.

10.3.2 The Two-Input NOR Gate W e first consider the C M O S gate that realizes the two-input N O R function

AB Y = A + B (10.21)

W e see that Y is to be low (PDN conduct ing) when A is h igh or B is h igh. Thus the P D N consists of two parallel N M O S devices wi th A and B as inputs (i.e., the circuit in Fig. 10.9a). For the P U N , w e note from the second express ion in Eq. (10.21) that 7 is to be h igh when A and B are both low. Thus the P U N consists of two series P M O S devices with A and B as the inputs (i.e., the circuit in Fig. 10.10b). Put t ing the P D N and the P U N together gives the C M O S N O R gate shown in Fig. 10.12. No te that extension to a higher n u m b er of inputs is straightforward: For each addit ional input, an N M O S transistor is added in parallel wi th QNA

and QNB, and a P M O S transistor is added in series with QPA and QPB.

10.3.3 The Two-Snput NAND Gate T h e two-input N A N D function is descr ibed by the Boolean expression

Y = AB = A+B (10.22)

To synthesize the P D N , w e consider the input combinat ions that require Y to be low: There is only one such combinat ion, namely , A and B bo th high. Thus , the P D N simply comprises two N M O S transistors in series (such as the circuit in Fig. 10.9b). T o synthesize the PUN, we consider the input combinat ions that result in Y being high. These are found from the

10.3 C M O S L O G I C - G A T E C I R C U I T S

VDD A

A 0 - 0 |

5 0 — 0 | QPB

a o — I QNA # o — | QNB

Y = A + B

- o f

FIGURE 1 0 . 1 2 A two-input CMOS NOR gate.

VDD A A

A o — o | QpA flo-o| QPB

A o 1 Q NA

B o 1 QNB

-OY

Y = AB FIGURE 1 0 . 1 3 A two-input CMOS NAND gate.

second expression in Eq . (10.22) as A low or B low. Thus , the P U N consists of two parallel P M O S transistors wi th A and B applied to their gates (such as the circuit in Fig. 10.10a). Putt ing the P D N and P U N together results in the C M O S N A N D gate implementa t ion shown in Fig. 10.13. N o t e that extension to a higher number of inputs is straightforward: For each addit ional input, w e add an N M O S transistor in series with QNA and QNB, and a P M O S tran-sistor in parallel with QPA and QPB.

10.3.4 A Complex Gate Consider next the m o r e complex logic function

Y = A{B + CD) (10.23)

Since Y = A(B + CD), w e see that Y should b e low for A high and simultaneously either B high or C and D bo th high, from which the P D N is directly obtained. T o obtain the P U N , we

9 6 6 i CHAPTER 10 D I G I T A L C M O S L O G I C C I R C U I T S

o 1 o 1 O c|

NMOS PMOS

(a) (b)

FIGURE 10 .11 Usual and alternative circuit symbols for MOSFETs.

digital-circuit designers. Figure 10.11 shows our usual symbols (left) and the corresponding "digi tal" symbols (right). Observe that the symbol for the P M O S transistor with a circle at the gate terminal is intended to indicate that the signal at the gate has to b e low for the device to be activated (i.e., to conduct) . Thus , in terms of logic-circuit terminology, the gate terminal of the P M O S transistor is an active low input. Besides indicating this property of P M O S devices, the digital symbols omit any indication of which of the device terminals is the source and which is the drain. This should, cause no difficulty at this stage of our study; simply r emember that for an N M O S transistor, the drain is the terminal that is at the higher voltage (current flows from drain to source), and for a P M O S transistor the source is the terminal that is at the higher voltage (current flows from source to drain). To be consistent with the litera-ture, w e shall henceforth use these modified symbols for M O S transistors in logic applica-tions, except in locations where our usual symbols help in understanding circuit operation.

10.3.2 The Two-Input NOR Gate W e first consider the C M O S gate that realizes the two-input N O R function

AB Y = A + B (10.21)

W e see that Y is to be low (PDN conduct ing) when A is h igh or B is h igh. Thus the P D N consists of two parallel N M O S devices wi th A and B as inputs (i.e., the circuit in Fig. 10.9a). For the P U N , w e note from the second express ion in Eq. (10.21) that 7 is to be h igh when A and B are both low. Thus the P U N consists of two series P M O S devices with A and B as the inputs (i.e., the circuit in Fig. 10.10b). Put t ing the P D N and the P U N together gives the C M O S N O R gate shown in Fig. 10.12. No te that extension to a higher n u m b er of inputs is straightforward: For each addit ional input, an N M O S transistor is added in parallel wi th QNA

and QNB, and a P M O S transistor is added in series with QPA and QPB.

10.3.3 The Two-Snput NAND Gate T h e two-input N A N D function is descr ibed by the Boolean expression

Y = AB = A+B (10.22)

To synthesize the P D N , w e consider the input combinat ions that require Y to be low: There is only one such combinat ion, namely , A and B bo th high. Thus , the P D N simply comprises two N M O S transistors in series (such as the circuit in Fig. 10.9b). T o synthesize the PUN, we consider the input combinat ions that result in Y being high. These are found from the

10.3 C M O S L O G I C - G A T E C I R C U I T S

VDD A

A 0 - 0 |

5 0 — 0 | QPB

a o — I QNA # o — | QNB

Y = A + B

- o f

FIGURE 1 0 . 1 2 A two-input CMOS NOR gate.

VDD A A

A o — o | QpA flo-o| QPB

A o 1 Q NA

B o 1 QNB

-OY

Y = AB FIGURE 1 0 . 1 3 A two-input CMOS NAND gate.

second expression in Eq . (10.22) as A low or B low. Thus , the P U N consists of two parallel P M O S transistors wi th A and B applied to their gates (such as the circuit in Fig. 10.10a). Putt ing the P D N and P U N together results in the C M O S N A N D gate implementa t ion shown in Fig. 10.13. N o t e that extension to a higher number of inputs is straightforward: For each addit ional input, w e add an N M O S transistor in series with QNA and QNB, and a P M O S tran-sistor in parallel with QPA and QPB.

10.3.4 A Complex Gate Consider next the m o r e complex logic function

Y = A{B + CD) (10.23)

Since Y = A(B + CD), w e see that Y should b e low for A high and simultaneously either B high or C and D bo th high, from which the P D N is directly obtained. T o obtain the P U N , we

Operação 9ísica do MOSFET

S

D G

Estrutura do MOSFET

Estrutura do MOSFET

9 5 0 ,v_ CHAPTER 1 0 D I G I T A L C M O S L O G I C C I R C U I T S

t e rms of product ion vo lume and societal impact) of electronic circuits. T o gain the mos t out of s tudying this chapter, the reader mus t b e thoroughly familiar wi th the M O S transistor. Thus , a review of Chapter 4 is r ecommended , and a careful study of Section 4.10 is a must!

" '" 10.1 DIGITAL CIRCUIT DESIGN: AN OVERVIEW

In this section, we build on the introduction to digital circuits presented in Section 1.7 and provide an overview of the subject. W e discuss the various technologies and logic-circuit families currently in use, consider the parameters employed to characterize the operation and performance of logic circuits, and finally ment ion the various styles for digital-system design.

10.1.1 Digital IC Technologies and Logic-Circuit Families The chart in Figure 10.1 shows the major IC technologies and logic-circuit families that are currently in use. The concept of a logic-circuit family perhaps needs a few words of expla-nation. M e m b e r s of each family are m a d e wi th the same technology, have a similar circuit structure, and exhibi t the same basic features. Each logic-circuit family offers a unique set of advantages and disadvantages . In the convent ional style of designing systems, one selects an appropriate logic family (e.g., T T L , C M O S , or E C L ) and at tempts to implement as much of the sys tem as possible using circuit modules (packages) that be long to this family. In this way, interconnection of the various packages is relatively straightforward. If, on the other hand, packages from more than one family are used, one has to design suitable interface cir-cuits. The selection of a logic family is based on such considerations as logic flexibility, speed of operation, availability of complex functions, noise immunity, operating-temperature range, power dissipation, and cost. W e wil l discuss some of these considerat ions in this chapter and the next. To begin with, w e m a k e some brief remarks on each of the four tech-nologies listed in the chart of Fig. 10.1 .

C M O S Al though shown as one of four poss ible technologies, this is not an indication of digital IC marke t share: C M O S technology is, by a large margin, the mos t dominant of all the IC technologies available for digital-circuit design. As ment ioned earlier, C M O S has replaced N M O S , which was employed in the early days of V L S I (in the 1970s). There are a number of reasons for this development , the mos t important of which is the m u c h lower power dissipat ion of C M O S circuits. C M O S has also replaced bipolar as the technology-of-choice in digital-system design, and has made possible levels of integration (or circuit-packing

Digital IC technologies and logic-circuit families

CMOS

Complementary Pseudo-NMOS Pass-transistor Dynamic CMOS logic logic

" f t Bipolar BiCMOS GaAs

TTL ECL

FIGURE 10.1 Digital IC technologies and logic-circuit families.

1 0 . 1 D I G I T A L C I R C U I T D E S I G N : A N O V E R V I E W 9 5 1

densi t ies) , and a r ange of appl ica t ions , nei ther of wh ic h wou ld h a v e been poss ib le wi th b i -polar technology. Furthermore, C M O S continues to advance, whereas there appear to be few innovations at the present t ime in bipolar digital circuits. S o m e of the reasons for C M O S displacing bipolar technology in digital applications are as follows:

1. C M O S logic circuits dissipate m u c h less power than bipolar logic circuits and thus one can pack more C M O S circuits on a chip than is possible wi th bipolar circuits. W e will have a lot more to say about power dissipation in the following sections.

2. The high input impedance of the M O S transistor al lows the designer to use charge storage as a means for the temporary storage of information in both logic and m e m o ry circuits. This technique cannot be used in bipolar circuits.

3 . The feature size (i.e., m i n i m u m channel length) of the M O S transistor has decreased dramatical ly over the years , with some recently reported des igns ut i l izing channel lengths as short as 0.06 pun. This permits very tight circuit pack ing and, correspond-ingly, very high levels of integration.

Of the var ious forms of C M O S , complementary C M O S circuits based on the inverter stud-ied in Sect ion 4 .10 are the mos t widely used. They are available both as small-scale inte-grated (SSI) circuit packages (containing 1-10 logic gates) and medium-sca le integrated (MSI) circuit packages ( 1 0 - 1 0 0 gates per chip) for assembl ing digital systems on printed-circuit boards . M o r e significantly, complementary C M O S is used in VLSI logic (with millions of gates per chip) and memory-circuit design. In some applications, complementary C M O S is supplemented by one (or both) of two other M O S logic circuit forms. These are pseudo-N M O S , so-named because of the similarity of its structure to N M O S logic, and pass-transistor logic, bo th of wh ich will b e studied in this chapter.

A fourth type of C M O S logic circuit util izes dynamic techniques to obtain faster circuit operation, whi le keeping the power dissipation very low. Dynami c C M O S logic represents an area of g rowing impor tance . Last ly, C M O S technology is used in the design of m e m o r y chips, as wil l b e detailed in Chapter 11 .

Bipolar T w o logic-circui t families based on the b ipolar junc t ion transistor are in some use at present : T T L and E C L . Trans is tor - t rans is tor logic (TTL or T 2 L ) was for m a n y years the mos t widely used logic-circuit family. Its decl ine was precipi ta ted by the advent of the VLSI era. T T L manufacturers , however , fought back wi th the in t roduct ion of l ow-power and h igh-speed vers ions . In these newer vers ions , the h igher speeds of opera t ion are m a d e possible by prevent ing the B J T from saturat ing and thus avoid ing the s low turnoff process of a saturated transistor. These nonsatura t ing vers ions of T T L util ize the Schot tky d iode discussed in Sect ion 3.8 and are called Schot tky T T L or variat ions of this name . Desp i te all these efforts, T T L is n o longer a significant logic-circui t family and will no t be s tudied in this book .

T h e other bipolar logic-circuit family in present use is emit ter-coupled logic (ECL) . It is based on the current-switch implementa t ion of the inverter, discussed in Section 1.7. The basic e lement of E C L is the differential B J T pair studied in Chapter 7. Because E C L is basi-cally a current-steering logic, and, correspondingly , also called c u r r e n t - m o d e logic (CML) , in which saturation is avoided, very high speeds of operat ion are possible . Indeed, of all the commercia l ly available logic-circuit families, E C L is the fastest. E C L is also used in V L S I circuit design when very high operating speeds are required and the designer is willing to accept h igher p o w e r dissipation and increased sil icon area. As such, E C L is considered an important specialty technology and will be briefly discussed in Chapter 11 .

Características principais de CIs

•  Margens de ruído

9 5 2 __• CHAPTER 10 D I G I T A L C M O S L O G I C C I R C U I T S

B i C M O S B iCMOS combines the high operating speeds possible with BJTs (because of their inherently higher transconductance) with the low power dissipation and other excellent charac-teristics of C M O S . Like C M O S , B i C M O S allows for the implementation of both analog and digital circuits on the same chip. (See the discussion of analog B i C M O S circuits in Chapter 6.) At present, B i C M O S is used to great advantage in special applications, including memory chips, where its high performance as a high-speed capacitive-current driver justifies the more complex process technology it requires. A brief discussion of B i C M O S is provided in Chapter 11.

G a l l i u m A r s e n i d e ( G a A s ) The high carrier mobil i ty in GaAs results in very h igh speeds of operat ion. This has been demonst ra ted in a number of digital IC chips util izing GaAs technology. It should be pointed out, however , that GaAs remains an "emerging technology," one that appears to have great potential but has not yet achieved such potential commer-cially. As such, it will not be studied in this book. Nevertheless , considerable material on GaAs devices and circuits, including digital circuits, can be found on the C D accompanying this book and on the b o o k ' s website .

10.1.2 Logic-Circuit Characterization The fol lowing parameters are usual ly used to character ize the operat ion and performance of a logic-circuit family.

N o i s e M a r g i n s The static operat ion of a logic-circuit family is character ized by the volt-age transfer characteristic (VTC) of its basic inverter. F igure 10.2 shows such a V T C and defines its four parameters ; V0H, V0L, VIH, and VIL. Note that VIH and VIL are defined as the points at which the slope of the V T C is - 1 . Also indicated is the definition of the threshold vol tage VM, or Vlh as we shall frequently call it, as the point at which v0 = vP Recal l that we discussed the V T C in its generic form in Section 1.7, and have also seen actual VTCs : in Section 4.10 for the C M O S inverter, and in Section 5.10 for the B J T inverter.

The r o b u s t n e s s of a logic-circuit family is determined by its ability to reject noise , and thus by the noise margins NHH and NML,

NMH=V0H-VIH (10.1)

NML=VIL-V0L (10.2)

FIGURE 10.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

10.1 D I G I T A L C I R C U I T D E S I G N : A N O V E R V I E W

OH

{(V0L+ VOH)

VOL

A ~H LPHL

1

1

1 9 0 % - V

— 10%—|—V- - J - !

I I I I — ^

-H h H L \<r ->| t T L H t

FIGURE 10 .3 Definitions of propagation delays and switching times of the logic inverter.

An ideal inverter is one for which NMH = NML = VDD/2, where VDD is the power-supply voltage. Further , for an ideal inverter, the threshold vol tage VM = VDD/2.

P r o p a g a t i o n D e l a y The dynamic performance of a logic-circuit family is character ized by the propagat ion delay of its basic inverter. F igure 10.3 illustrates the definition of the low-to-high propagat ion delay (tPLH) and the high- to- low propagat ion delay (tPHL). The inverter propagat ion delay (tP) is defined as the average of these two quantit ies:

tp — PLH + t„ L) (10.3)

Obviously, the shorter the propagat ion delay, the higher the speed at which the logic-circuit family can be operated.

Power D i s s i p a t i o n Power dissipation is an important issue in digital-circuit design. The need to min imize the gate power dissipation is mot ivated by the desire to pack an ever-increasing number of gates on a chip, which in turn is mot ivated by space and economic considerat ions. In general , however , modern digital systems util ize large numbers of gates and m e m o ry cells, and thus to keep the total power requirement within reasonable bounds , the power dissipat ion per gate and per memor y cell should be kept as low as possible . This is particularly the case for portable, bat tery-operated equipment such as cellular phones and personal digital assistants (PDAs) .

There are two types of power dissipation in a logic gate: static and dynamic . Static power refers to the power that the gate dissipates in the absence of switching action. It results from the presence of a path in the gate circuit be tween the power supply and ground in one or bo th of its two states (i.e., with the output either low or high). Dynamic power , on the other hand, occurs only when the gate is switched: A n inverter operated from a power supply VDD, and driving a load capaci tance C, dissipates dynamic power PD,

fcvL (10.4)

9 5 2 __• CHAPTER 10 D I G I T A L C M O S L O G I C C I R C U I T S

B i C M O S B iCMOS combines the high operating speeds possible with BJTs (because of their inherently higher transconductance) with the low power dissipation and other excellent charac-teristics of C M O S . Like C M O S , B i C M O S allows for the implementation of both analog and digital circuits on the same chip. (See the discussion of analog B i C M O S circuits in Chapter 6.) At present, B i C M O S is used to great advantage in special applications, including memory chips, where its high performance as a high-speed capacitive-current driver justifies the more complex process technology it requires. A brief discussion of B i C M O S is provided in Chapter 11.

G a l l i u m A r s e n i d e ( G a A s ) The high carrier mobil i ty in GaAs results in very h igh speeds of operat ion. This has been demonst ra ted in a number of digital IC chips util izing GaAs technology. It should be pointed out, however , that GaAs remains an "emerging technology," one that appears to have great potential but has not yet achieved such potential commer-cially. As such, it will not be studied in this book. Nevertheless , considerable material on GaAs devices and circuits, including digital circuits, can be found on the C D accompanying this book and on the b o o k ' s website .

10.1.2 Logic-Circuit Characterization The fol lowing parameters are usual ly used to character ize the operat ion and performance of a logic-circuit family.

N o i s e M a r g i n s The static operat ion of a logic-circuit family is character ized by the volt-age transfer characteristic (VTC) of its basic inverter. F igure 10.2 shows such a V T C and defines its four parameters ; V0H, V0L, VIH, and VIL. Note that VIH and VIL are defined as the points at which the slope of the V T C is - 1 . Also indicated is the definition of the threshold vol tage VM, or Vlh as we shall frequently call it, as the point at which v0 = vP Recal l that we discussed the V T C in its generic form in Section 1.7, and have also seen actual VTCs : in Section 4.10 for the C M O S inverter, and in Section 5.10 for the B J T inverter.

The r o b u s t n e s s of a logic-circuit family is determined by its ability to reject noise , and thus by the noise margins NHH and NML,

NMH=V0H-VIH (10.1)

NML=VIL-V0L (10.2)

FIGURE 10.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

10.1 D I G I T A L C I R C U I T D E S I G N : A N O V E R V I E W

OH

{(V0L+ VOH)

VOL

A ~H LPHL

1

1

1 9 0 % - V

— 10%—|—V- - J - !

I I I I — ^

-H h H L \<r ->| t T L H t

FIGURE 10 .3 Definitions of propagation delays and switching times of the logic inverter.

An ideal inverter is one for which NMH = NML = VDD/2, where VDD is the power-supply voltage. Further , for an ideal inverter, the threshold vol tage VM = VDD/2.

P r o p a g a t i o n D e l a y The dynamic performance of a logic-circuit family is character ized by the propagat ion delay of its basic inverter. F igure 10.3 illustrates the definition of the low-to-high propagat ion delay (tPLH) and the high- to- low propagat ion delay (tPHL). The inverter propagat ion delay (tP) is defined as the average of these two quantit ies:

tp — PLH + t„ L) (10.3)

Obviously, the shorter the propagat ion delay, the higher the speed at which the logic-circuit family can be operated.

Power D i s s i p a t i o n Power dissipation is an important issue in digital-circuit design. The need to min imize the gate power dissipation is mot ivated by the desire to pack an ever-increasing number of gates on a chip, which in turn is mot ivated by space and economic considerat ions. In general , however , modern digital systems util ize large numbers of gates and m e m o ry cells, and thus to keep the total power requirement within reasonable bounds , the power dissipat ion per gate and per memor y cell should be kept as low as possible . This is particularly the case for portable, bat tery-operated equipment such as cellular phones and personal digital assistants (PDAs) .

There are two types of power dissipation in a logic gate: static and dynamic . Static power refers to the power that the gate dissipates in the absence of switching action. It results from the presence of a path in the gate circuit be tween the power supply and ground in one or bo th of its two states (i.e., with the output either low or high). Dynamic power , on the other hand, occurs only when the gate is switched: A n inverter operated from a power supply VDD, and driving a load capaci tance C, dissipates dynamic power PD,

fcvL (10.4)


•  Delay de propagação

Power RequirementsEvery IC requires a certain amount of electrical power to operate. Thispower is supplied by one or more power-supply voltages connected to thepower pin(s) on the chip labeled (for TTL) or (for MOS devices).

The amount of power that an IC requires is determined by the current,(or ), that it draws from the (or ) supply, and the actual power

is the product For many ICs, the current drawn from the supplyvaries depending on the logic states of the circuits on the chip. For example,Figure 8-3(a) shows a NAND chip where all of the gate outputs are HIGH.Thecurrent drain on the supply for this case is called Likewise, Figure8-3(b) shows the current when all of the gate outputs are LOW. This currentis called The values are always measured with the outputs open circuit(no load) because the size of the load will also have an effect on .

In some logic circuits, and will be different values. For thesedevices, the average current is computed based on the assumption that gateoutputs are LOW half the time and HIGH half the time.

ICC(avg) =ICCH + ICCL

2

ICCLICCH

ICCH

ICCL.

ICCH.VCC

ICC * VCC.VDDVCCIDDICC

VDDVCC

492 CHAPTER 8/INTEGRATED-CIRCUIT LOGIC FAMILIES

Input 1

Output 1

0

0

tPHL tPLH

50%

50%

t

FIGURE 8-2 Propagationdelays.

011

011

011

+VCC

ICCH

(a)

1

1

1

(b)

+VCC

ICCL

0

0

0

111

111

111

FIGURE 8-3 and .ICCLICCH

TOCCMC08_0131725793.QXD 12/17/2005 3:58 PM Page 492


•  Dissipação de potência (está+ca e dinâmica)

•  Produto atraso-‐potência

•  Área do silício

•  Fan-‐in e fan-‐out

PD = f V C2DD

DP = PDtP

of the notch on one end, which is used to locate pin 1. Some DIPs use a smalldot on the top surface of the package to locate pin 1. The leads extendstraight out of the DIP package so that the IC can be plugged into an ICsocket or inserted into holes drilled through a printed circuit board.The spac-ing between pins (lead pitch) is typically 100 mils (a mil is a thousandth of aninch). DIP packages are still the most popular package for prototyping, bread-boarding, and educational experimentation.

Nearly all new circuit boards that are produced using automated manufac-turing equipment have moved away from using DIP packages whose leads areinserted through holes in the board. New manufacturing methods use surface-mount technology, which places an IC onto conductive pads on the surface ofthe board. They are held in place by a solder paste, and the entire board isheated to create a soldered connection. The precision of the placement ma-chine allows for very tight lead spacing. The leads on these surface-mountpackages are bent out from the plastic case, providing adequate surface area

496 CHAPTER 8/INTEGRATED-CIRCUIT LOGIC FAMILIES

Pins on allfour sides Chipped

corner

Pin 2

Pin 1

Pin 28Pin 24

(c)

28-pin PLCC(J-lead)

socket or surface-mount

Notch

Pin 1

(a)

24-pin DIP

Pin 12

Pins on allfour sides

Pin 1

(d)

48-pin QFP(gull-wing)

surface-mount

Pin 12

Pin 13

Pin 48

Pin 33

Pin 32

Pin 1

(b)

16-pin SOIC(gull-wing)

surface-mount

Pin 8

Bevel

Pin 9

Pin 13

6

5

4

3

2

1A B C D E F G H J K L M N P R T

1

2

3

4

5

6

A B C D E F G H J K L M N P R T

13.5 mm

96-pin LFBGAsurface mount

(e)

5.5 mm

0.8 mm

1.5 mmmax.

FIGURE 8-6 Common IC packages. (Courtesy of Texas Instruments)

TOCCMC08_0131725793.QXD 12/17/2005 3:58 PM Page 496

Alguns CIs •  7402 – 4 portas NOR

•  7404 – 6 portas NOT

•  7408 – 4 portas AND de 2 entradas cada

•  7410 – 3 portas NAND de 3 entradas

•  7432 – 4 portas OR de 2 entradas cada

•  Entre outros…

SITUAÇÃO TABELA DA

VERDADE

EXPRESSÃO SIMPLIFICADA CIRCUITO

Projeto

3 portas NOT : 1 CI 7404 2 portas XNOR : 1 CI 74266 1 porta XOR: 1 CI 7486 9 portas AND (2 entradas): 3 CIs 7408 1 porta AND (3 entradas): 1 CI 7411 14 portas OR (2 entradas): 4 CIs 7432

4511 (BCD to 7-‐segment decoder driver)

SituaçãoTabela verdade

Expressãosimplificada

Circuito

http://8bitspaghetti.com/

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